參數(shù)資料
型號(hào)： S71WS512N80BFIZZ0
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特
文件頁(yè)數(shù)： 3/142頁(yè)
文件大小： 1996K
代理商： S71WS512N80BFIZZ0
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
3
A d v a n c e I n f o r m a t i o n
TABLE OF CONTENTS
S71WS512NE0BFWZZ
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MCP Block Diagram of S71WS512NE0BFWZZ ...........................................6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagram of S71WS512NE0BFWZZ ..........................................7
Special Package Handling Instructions ........................................................8
Pin Description ..................................................................................................8
Logic Symbol .....................................................................................................9
Device Bus Operation .......................................................................................10
Table 1. Device Bus Operations ........................................... 10
Pin Capacitance ...................................................................................................12
Physical Dimensions TBD . . . . . . . . . . . . . . . . . . 13
XXX .........................................................................................................................13
S29WSxxxN MirrorBit Flash Family
For Multi-chip Products (MCP)
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 14
General Description . . . . . . . . . . . . . . . . . . . . . . . . 16
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 19
Block Diagram ....................................................................................................19
Block Diagram of Simultaneous Operation Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 21
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .23
Table 2. Device Bus Operations ........................................... 23
Requirements for Asynchronous Read Operation (Non-Burst) ..........23
Requirements for Synchronous (Burst) Read Operation ......................24
Table 3. Address Dependent Additional Latency ..................... 24
Continuous Burst ...........................................................................................24
8-, 16-, and 32-Word Linear Burst with Wrap Around ......................25
Table 4. Burst Address Groups ............................................ 25
8-, 16-, and 32-Word Linear Burst without Wrap Around ................25
Configuration Register ......................................................................................25
Handshaking ..........................................................................................................25
Simultaneous Read/Write Operations with Zero Latency ...................26
Writing Commands/Command Sequences ................................................26
Unlock Bypass Mode ....................................................................................26
Accelerated Program/Erase Operations .....................................................26
Write Buffer Programming Operation .........................................................27
Autoselect Mode ................................................................................................28
Advanced Sector Protection and Unprotection .......................................29
Persistent Mode Lock Bit ............................................................................29
Password Mode Lock Bit .............................................................................30
Sector Protection ...............................................................................................30
Persistent Sector Protection ..........................................................................30
Persistent Protection Bit (PPB) ...................................................................31
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode ..............................................................................................31
Dynamic Protection Bit (DYB) ....................................................................31
Table 5. Sector Protection Schemes ..................................... 32
Password Sector Protection ............................................................................33
64-bit Password ...............................................................................................33
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector
Protection Mode .............................................................................................33
Lock Register .......................................................................................................34
Table 6. Lock Register ........................................................ 34
Hardware Data Protection Mode .................................................................34
Write Protect (WP#) ...................................................................................34
Low V
CC
Write Inhibit .................................................................................34
Write Pulse “Glitch” Protection ...............................................................35
Logical Inhibit ...................................................................................................35
Power-Up Write Inhibit ............................................................................... 35
Standby Mode ...................................................................................................... 35
Automatic Sleep Mode .....................................................................................35
RESET#: Hardware Reset Input ................................................................ 35
Output Disable Mode ...................................................................................36
SecSi (Secured Silicon) Sector Flash Memory Region ..........................36
Factory Locked: Factor SecSi Sector Programmed and Protected At
the Factory .......................................................................................................36
Table 7. SecSi
TM
Sector Addresses ........................................37
Customer SecSi Sector .................................................................................37
SecSi Sector Protection Bit .........................................................................37
Common Flash Memory Interface (CFI) . . . . . . 37
Table 8. CFI Query Identification String ................................ 38
Table 9. System Interface String ......................................... 38
Table 10. Device Geometry Definition ................................... 39
Table 11. Primary Vendor-Specific Extended Query ................39
Table 12. Sector Address / Memory Address Map for the WS256N
........................................................................................41
Command Definitions . . . . . . . . . . . . . . . . . . . . . .49
Reading Array Data ...........................................................................................49
Set Configuration Register Command Sequence .....................................49
Read Configuration Register Command Sequence ..................................50
Figure 1. Synchronous/Asynchronous State Diagram.............. 50
Read Mode Setting .........................................................................................50
Programmable Wait State Configuration ...............................................50
Table 13. Programmable Wait State Settings .........................51
Programmable Wait State ............................................................................51
Boundary Crossing Latency .........................................................................51
Set Internal Clock Frequency ......................................................................51
Table 14. Wait States for Handshaking .................................51
Handshaking ......................................................................................................51
Burst Sequence ...............................................................................................52
Burst Length Configuration .........................................................................52
Table 15. Burst Length Configuration ................................... 52
Burst Wrap Around ......................................................................................52
Burst Active Clock Edge Configuration ..................................................52
RDY Configuration ........................................................................................52
RDY Polarity ....................................................................................................52
Configuration Register ......................................................................................53
Table 16. Configuration Register ..........................................53
Reset Command .................................................................................................53
Autoselect Command Sequence ....................................................................54
Table 17. Autoselect Addresses ...........................................54
Enter SecSi Sector/Exit SecSi Sector Command Sequence ................55
Word Program Command Sequence ...........................................................55
Write Buffer Programming Command Sequence .....................................56
Table 18. Write Buffer Command Sequence .......................... 56
Figure 2. Write Buffer Programming Operation ...................... 57
Unlock Bypass Command Sequence ........................................................57
Figure 3. Program Operation............................................... 58
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S71WS512N80BFIZZ3 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ0 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ2 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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相關(guān)代理商/技術(shù)參數(shù)
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S71WS512N80BFIZZ2 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFIZZ3 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ0 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ2 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ3 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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