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參數(shù)資料
| 型號(hào)： | S71WS512N80BFIZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 55/142頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BFIZZ0 |
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
55
A d v a n c e I n f o r m a t i o n
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the bank was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, eight
word electronic serial number (ESN). The system can access the SecSi Sector re-
gion by issuing the three-cycle Enter SecSi Sector command sequence. The
device continues to access the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command
sequence returns the device to normal operation. The SecSi Sector is not acces-
sible when the device is executing an Embedded Program or embedded Erase
algorithm. The "
Command Definition Summary
" section shows the address and
data requirements for both command sequences.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is
not
required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin.
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh
(BA) + 0Fh
2230 (WS256N)
2200
DQ15 - DQ8 = 0
DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
DQ6 -Customer Lock Bit
1 = Locked, 0 = Not Locked
DQ5 - Handshake Bit
1 = Reserved,
0 = Standard Handshake
DQ4 & DQ3 - WP# Protection Boot Code
00 = WP# Protects both Top Boot and
Bottom Boot Sectors,
01 = Reserved,
10 = Reserved
11 = Reserved
DQ2 = 0
DQ1 - DYB Power up state
(DQ1 = Lock Register DQ4)
1 = Unlocked (user option)
0 = Locked (default)
DQ0 - PPB Eraseability
(DQ0 = Lock Register DQ3)
1 = Erase allowed
0 = Erase disabled
Indicator Bits
(BA) + 03h
Table 17. Autoselect Addresses
Description
Address
Read Data
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| S71WS512N80BFIZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BFIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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