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參數(shù)資料
| 型號： | S71WS512N80BFIZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 106/142頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BFIZZ0 |
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106
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004
P r e l i m i n a r y
FUNCTIONAL DESCRIPTION (Continued)
Burst Read Suspend
Burst read operation can be suspended by OE# High pulse. During burst read
operation, OE# brought to High suspends burst read operation. Once OE# is
brought to High with the specified set up time against clock where the data being
suspended, the device internal counter is suspended, and the data output become
high impedance after specified time duration. It is inhibited to suspend the first
data out at the beginning of burst read.
OE# brought to Low resumes burst read operation. Once OE# is brought to Low,
data output become valid after specified time duration, and internal address
counter is reactivated. The last data out being suspended as the result of OE#=H
and first data out as the result of OE#=L are the from the same address.
Burst Write Suspend
Burst write operation can be suspended by WE# High pulse. During burst write
operation, WE# brought to High suspends burst write operation. Once WE# is
brought to High with the specified set up time against clock where the data being
suspended, device internal counter is suspended, data input is ignored. It is
inhibited to suspend the first data input at the beginning of burst write.
WE# brought to Low resumes burst write operation. Once WE# is brought to Low,
data input become valid after specified time duration, and internal address counter
is reactivated. The write address of the cycle where data being suspended and
the first write address as the result of WE#=L are the same address.
Burst write suspend function is available when the device is operating in WE#
level controlled burst write only.
Q
2
DQ
OE#
CLK
Q
1
t
AC
t
CKQX
t
OLZ
t
AC
Q
2
t
CKQX
t
AC
Q
3
t
CKQX
t
AC
t
CKOH
t
OSCK
t
CKOH
t
OSCK
t
OHZ
WAIT#
t
CKTV
Q
4
DQ
WE#
D
1
t
DHCK
t
DSCK
D-
t
DSCK
D
2
t
DHCK
D-
t
DSCK
D
3
t
DHCK
t
DSCK
t
CKWH
t
WSCK
t
CKWH
t
WSCK
D
2
D
4
WAIT#
High
CLK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BFIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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