參數(shù)資料
型號(hào): S71GL512NB0
廠商: Spansion Inc.
英文描述: Stacked Multi-chip Product (MCP)
中文描述: 堆疊式多芯片產(chǎn)品(MCP)
文件頁數(shù): 144/147頁
文件大?。?/td> 1655K
代理商: S71GL512NB0
144
pSRAM Type 7
pSRAM_Type07_13_A0 May 4, 2004
A d v a n c e I n f o r m a t i o n
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Note:
The t
C2LH
specifies after V
DD
reaches specified minimum level.
Figure 47. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
Figure 48. Power-up Timing #1
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
t
WC
t
BW
OE#
UB#, LB#
t
BA
WRITE ADDRESS
t
AS
t
RC
WRITE DATA INPUT
t
DS
t
BHZ
t
OH
t
AA
READ ADDRESS
t
DH
t
BLZ
t
OH
READ DATA OUTPUT
t
BHZ
Low
t
ASO
t
OHAH
t
OHAH
t
OES
t
WHOL
t
WR
t
C2LH
CE1#
V
DD
V
DD
min
0V
CE2
t
CHH
t
CHS
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