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參數(shù)資料
| 型號： | S71GL512NB0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁數(shù)： | 129/147頁 |
| 文件大?。?/td> | 1655K |
| 代理商： | S71GL512NB0 |
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May 4, 2004 pSRAM_Type07_13_A0
pSRAM Type 7
129
A d v a n c e I n f o r m a t i o n
The default state is Sleep and it is the lowest power consumption but all data will
be lost once CE2 is brought to Low for Power Down. It is not required to program
to Sleep mode after power-up.
Power Down Program Sequence
The program requires total 6 read/write operation with unique address. Between
each read/write operation requires that device be in standby mode. Following
table shows the detail sequence.
The first cycle is to read from most significient address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the program is
cancelled and the data written by the second or third cycle is valid as a normal
write operation.
The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is
don’t-care. If the forth or fifth cycle is written into different address, the program
is also cancelled but write data may not be wrote as normal write operation.
The last cycle is to read from specific address key for mode selection.
Once this program sequence is performed from a Partial mode to the other Partial
mode, the written data stored in memory cell array may be lost. So, it should per-
form this program prior to regular read/write operation if Partial mode is used.
Address Key
The address key has following format.
Cycle #
Operation
Address
Data
1st
Read
3FFFFFh (MSB)
Read Data (RDa)
2nd
Write
3FFFFFh
RDa
3rd
Write
3FFFFFh
RDa
4th
Write
3FFFFFh
Don’t Care (X)
5th
Write
3FFFFFh
X
6th
Read
Address Key
Read Data (RDb)
Mode
Address
32M
64M
A21
A20
A19
A18 - A0
Binary
Sleep (default)
Sleep (default)
1
1
1
1
3FFFFFh
4M Partial
N/A
1
1
0
1
37FFFFh
8M Partial
8M Partial
1
0
1
1
2FFFFFh
N/A
16M Partial
1
0
0
1
27FFFFh
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| S71GS256NC0BFWAK0 | 128N based MCPs |
| S71GS128NB0 | 128N based MCPs |
| S71GS128NB0BAWAK0 | 128N based MCPs |
| S71GS128NB0BAWAK2 | 128N based MCPs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71GL512NC0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Product (MCP) |
| S71GL-N | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| S71GL-N_08 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| S71GLXXXNC0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Product (MCP) |
| S71GS128NB0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128N based MCPs |
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