參數(shù)資料
型號: S6D0110
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 132 RGB Source & 176 Gate Driver With Internal GRAM FOR 65,536 Colors TFT-LCD
中文描述: 132的RGB源
文件頁數(shù): 53/108頁
文件大?。?/td> 595K
代理商: S6D0110
S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD
Preliminary
53
RESET FUNCTION
The S6D0110 is internally initialized by RESET input. The reset input must be held for at least 1 ms. Do not access
the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied
(10 ms).
Instruction Set Initialization
1. Start oscillation executed
2. Driver output control (NL4–0 = 10101, SS = 0, CS = 0)
3. B-pattern waveform AC drive (FLD1-0 = 01, B/C = 0, EOR = 0, NW5–0 = 00000)
4. Power control 1 (SAP2-0 = 000, BT2-0 = 000, DC2–0 = 000, AP2–0 = 000: LCD power off, SLP = 0, STB = 0:
Standby mode off)
5. Power control 2 (CAD = 0, VRN4-0 = 00000, VRP4-0 = 00000)
6. Entry mode set (HWM = 0, I/D1-0 = 11: Increment by 1, AM = 0: Horizontal move, LG2–0 = 000: Replace mode)
7. Compare register (CP15–0: 0000000000000000)
8. Display control (PT1-0 = 00, VLE2–1 = 00: No vertical scroll, SPT = 0, GON = 0, DTE = 0, CL = 0: 65536 color
mode, REV = 0, D1–0 = 00: Display off)
9. Display control (FP3-0=0101, BP3-0=0011, BLP13-0=0010, BLP23-0=0010)
10. Frame cycle control (NO1-0 = 00, SDT1-0 = 00, EQ1-0 = 00: no equalizer, DIV1-0 = 00: 1-divided clock, RTN3-0
= 0000: 16 clock cycle in 1H period)
11. Power control 3 (VC2-0 = 000)
12. Power control 4 (VRL3-0 = 0000, PON=0, VRH3-0 = 0000)
13. Power control 5 (VCOMG = 0, VDV4-0 = 00000, VCM4-0 = 00000)
14. Gate scanning starting position (SCN4-0 = 00000)
15. Vertical scroll (VL7–0 = 0000000)
16. 1st screen division (SE17-10 = 11111111, SS17-10 = 00000000)
17. 2nd screen division (SE27-20 = 11111111, SS27-20 = 00000000)
18. Horizontal RAM address position (HEA7-0 = 10000011, HSA7-0 = 00000000)
19. Vertical RAM address position (VEA7-0 = 10101111, VSA7-0 = 00000000)
20. RAM write data mask (WM15–0 = 0000h: No mask)
21. RAM address set (AD15–0 = 0000h)
22. Gamma control
(PKP02–00 = 000, PKP12–10 = 000, PKP22–20 = 000, PKP32–30 = 000,
PK42–40 = 000, PKP52–50 = 000, PRP02–00 = 000, PRP12–10 = 000)
(PKN02–00 = 000, PKN12–10 = 000, PKN22–20 = 000, PKN32–30 = 000,
PKN42–40 = 000, PKN52–50 = 000, PRN02–00 = 000, PRN12–10 = 000)
GRAM Data Initialization
GRAM is not automatically initialized by reset input but must be initialized by software while display is off (D1–0 =
00).
Output Pin Initialization
1. LCD driver output pins (Source output) : Output VSS level
(Gate output) : Output Vgoff level
2. Oscillator output pin (OSC2): Outputs oscillation sign
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