參數(shù)資料
型號(hào): S6D0110
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 132 RGB Source & 176 Gate Driver With Internal GRAM FOR 65,536 Colors TFT-LCD
中文描述: 132的RGB源
文件頁(yè)數(shù): 44/108頁(yè)
文件大?。?/td> 595K
代理商: S6D0110
132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD
S6D0110
Preliminary
44
Frame Cycle Control (R0Bh)
R/W
W
RS
1
DB15
NO1
DB14
NO0
DB13
SDT1
DB12
SDT0
DB11
EQ1
DB10
EQ0
DB9
DIV1
DB8
DIV0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
RTN3
DB2
RTN2
DB1
RTN1
DB0
RTN0
RTN3-0:
Set the 1H period.
RTN3
0
0
0
.
.
.
1
1
RTN2
0
0
0
.
.
.
1
1
RTN1
0
0
1
.
.
.
1
1
RTN0
0
1
0
.
.
.
0
1
Clock cycles per raster row
16
17
18
.
.
.
30
31
DIV1-0:
Set the division ratio of clocks for internal operation (DIV1-0). Internal operations are driven by clocks, which
are frequency divided according to the DIV1-0 setting. Frame frequency can be adjusted along with the 1H period
(RTN3-0). When changing number of the drive cycle, adjust the frame frequency. For details, see the Frame
Frequency Adjustment Function section.
DIV1
0
0
1
1
DIV0
0
1
0
1
Division Ratio
1
2
4
8
Internal operation clock frequency
fosc/1
fosc/2
fosc/4
fosc/8
*fosc = R-C oscillation frequency
EQ1-0:
EQ period is sustained for the number of clock cycle which is set on EQ1-0. When VcomL<0, set these bits
as “ 00” for preventing the abnormal function.
EQ1
0
0
1
1
EQ0
0
1
0
1
EQ period
No EQ
1 clock cycle
2 clock cycle
3 clock cycle
Frame Frequency =
f
OSC
Clock cycles per raster-row x division ratio x (Line+B)
[Hz]
f
OSC
: R-C oscillation frequency
Line: Number of raster-rows (NL bit)
Clock cycles per raster-row: RTN bit
Division ratio: DIV bit
B: Blank period(Back porch + Front Porch)
Figure 10. Formula for the frame frequency
相關(guān)PDF資料
PDF描述
S6D0114 132 RGB X 176 DOT 1-CHIP DRIVER IC WITH INTERNAL GRAM FOR 262,144 Colors TFT-LCD
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