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參數(shù)資料
| 型號： | S29PL256N65FAW002 |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁模式閃存 |
| 文件頁數(shù)： | 77/85頁 |
| 文件大?。?/td> | 940K |
| 代理商： | S29PL256N65FAW002 |
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November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit Flash Family
75
P r e l i m i n a r y
12.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables
12.3
–
12.6
) within that bank. All reads outside of the
CFI address range, within the bank, return non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the
S pansion Low Lev el Driv er User’s Guide
( available at
www.amd.com
and
www.fujitsu.com
) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*((UINT16 *)bank_addr + 0x555) = 0x0098; /* write CFI entry command */
/* Example: CFI Exit command */
*((UINT16 *)bank_addr + 0x000) = 0x00F0; /* write cfi exit command */
Notes:
1.
2.
3.
See (
Table 7.1
) for description of bus operations.
All values are in hexadecimal.
Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
and password verify commands, and any cycle reading at RD(0)
and RD(1).
Data bits DQ15 – DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3 – PWD0.
Unless otherwise noted, these address bits are
don’t cares:
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See
Autoselect
.
10. The data is 0000h for an unlocked sector and 0001h for a locked
sector.
11. Device IDs: PL256N = 223Ch; PL127N = 2220h;
PL129N = 2221h.
12. See
Autoselect
.
13. The Unlock Bypass command sequence is required prior to this
command sequence.
14. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
4.
5.
6.
7.
8.
9.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
17. The entire four bus-cycle sequence must be entered for which
portion of the password.
18. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
19. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
20. Command is valid when device is ready to read array data or
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
21. The entire four bus-cycle sequence must be entered for which
portion of the password.
22. The ALL PPB ERASE command pre-programs all PPBs before
erasure to prevent over-erasure of PPBs.
23. WP#/ACC must be at VHH during the entire operation of this
command.
24. Command sequence resets device for next command after write-
to-buffer operation.
25. Entry commands are needed to enter a specific mode to enable
instructions only available within that mode.
26. If both the Persistent Protection Mode Locking Bit and the
password Protection Mode Locking Bit are set a the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode.
27. The Exit command must be issued to reset the device into read
mode. Otherwise the device hangs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29PL256N65FAW003 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FAWW00 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FAWW02 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FAWW03 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FFI000 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29PL256N65FAW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FAWW00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FAWW02 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FAWW03 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N65FFI000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
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