參數(shù)資料
型號(hào): S29PL256N65FAW002
廠商: Spansion Inc.
英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述: 256/128/128字節(jié)(16/8/8 M中的x 16位),3.0伏的CMOS只同步讀/寫,頁模式閃存
文件頁數(shù): 35/85頁
文件大小: 940K
代理商: S29PL256N65FAW002
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit Flash Family
33
P r e l i m i n a r y
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. See
Write Operation Status
for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
The following is a C source code example of using the chip erase function. Refer to the
Span-
sion Low Level Driver User’s Guide
(available on
www.amd.com
and
www.fujitsu.com
) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended */
*((UINT16 *)base_addr + 0x555) = 0x00AA; /* write unlock cycle 1 */
*((UINT16 *)base_addr + 0x2AA) = 0x0055; /* write unlock cycle 2 */
*((UINT16 *)base_addr + 0x555) = 0x0080; /* write setup command */
*((UINT16 *)base_addr + 0x555) = 0x00AA; /* write additional unlock cycle 1 */
*((UINT16 *)base_addr + 0x2AA) = 0x0055; /* write additional unlock cycle 2 */
*((UINT16 *)base_addr + 0x000) = 0x0010; /* write chip erase command */
7.4.5 Erase Suspend/ Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. The bank address is re-
quired when writing this command. This command is valid only during the sector erase operation,
including the minimum t
SEA
time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation.
When the Erase Suspend command is written during the sector erase operation, the device re-
quires a maximum of t
ESL
(erase suspend latency) to suspend the erase operation. However,
when the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice
erase suspends
all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to
Table 7.18
for information on these status bits.
Software Functions and Sample Code
Table 7.10 Chip Erase
(LLD Function = lld_ ChipEraseCmd)
Cycle
Description
Operation
Word Address
Data
1
Unlock
Write
Base + 555h
00AAh
2
Unlock
Write
Base + 2AAh
0055h
3
Setup
Command
Write
Base + 555h
0080h
4
Unlock
Write
Base + 555h
00AAh
5
Unlock
Write
Base + 2AAh
0055h
6
Chip Erase
Command
Write
Base + 555h
0010h
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