參數(shù)資料
型號(hào): S29PL256N65FAW002
廠商: Spansion Inc.
英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述: 256/128/128字節(jié)(16/8/8 M中的x 16位),3.0伏的CMOS只同步讀/寫,頁(yè)模式閃存
文件頁(yè)數(shù): 66/85頁(yè)
文件大?。?/td> 940K
代理商: S29PL256N65FAW002
64
S29PL-N MirrorBit Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
11.8
AC Characteristics
11.8.1 Read Operations
Notes:
1.
2.
3.
Not 100% tested.
See
Figure 11.3
and
Table 11.1
for test specifications
Measurements performed by placing a 50 ohm termination on the data pin with a bias of V
CC
/2. The time from OE#
high to the data bus driven to V
CC
/2 is taken as t
DF
.
For 70pf Output Load Capacitance, 2 ns is added to the above t
ACC
,t
CE
,t
PACC
,t
OE
values for all speed grades
CE1# and CE2# for the PL129N.
4.
5.
11.8.2 Read Operation Timing Diagrams
Figure 11.6 Read Operation Timings
Parameter
Description
(Notes)
Test Setup
Speed Options
JEDEC
Std.
65
70
80
Unit
t
AVAV
t
RC
Read Cycle Time (
1
)
Min
65
70
80
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
65
70
80
ns
t
ELQV
t
CE
Chip Enable to Output Delay (
5
)
OE# = V
IL
Max
65
70
80
ns
t
PACC
Page Access Time
Max
25
30
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (
3
)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (
1
,
3
)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (
3
)
Min
5
ns
t
OEH
Output Enable Hold Time (
1
)
Read
Min
0
ns
Toggle and Data# Polling
Min
10
ns
t
OH
t
CE
Data
WE#
Addresses
CE#
OE#
HIGH Z
Valid Data
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
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