參數(shù)資料
型號(hào)： S2065
廠商： Applied Micro Circuits Corp.
英文描述： Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器)
中文描述： 四串行設(shè)備，配有雙背板的I / O（帶雙傳送接收串行的I / O的四收發(fā)器）
文件頁(yè)數(shù)： 12/37頁(yè)
文件大?。?/td> 381K
代理商： S2065
12
S2065
QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision G
Reference Clock Input
The reference clock must be provided from a low
jitter clock source. The frequency of the received
data stream (divided-by-10 or 20) must be within 200
ppm of the reference clock to ensure reliable locking
of the receiver PLL. A single reference clock is pro-
vided to both the transmitter and the receiver of the
S2065.
Serial to Parallel Conversion
Once bit synchronization has been attained by the
S2065 CRU, the S2065 must synchronize to the 10
bit word boundary. Word synchronization in the
S2065 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2065 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2065 will detect and align to a K28.5
anywhere in the data stream. Two modes of opera-
tion are supported. For NORMAL mode operation,
the presence of a K28.5 is indicated for each chan-
nel by the assertion of the EOFx signal.
For CHANNEL LOCK operation, the S2065 must
provide an additional level of synchronization to en-
sure that differences in delay encountered by the
four channels do not result in parallel output data
from each channel leading or lagging by one parallel
clock cycle. When in CHANNEL LOCK mode, asser-
tion of SOFA results in the K28.5 being transmitted
simultaneously on all four channels. Each receiver
provides a FIFO buffer and adjusts the delay through
this buffer to ensure that the first data following the
K28.5 is output simultaneously from the receiver on
the parallel interface. The reception of a K28.5 char-
acter is indicated on the EOFA signal. Table 8 de-
tails the function of the EOF, KFLAG, and ERR pins
in status reporting. For CHANNEL LOCK operation,
a single output clock,
RCAP/N, is provided synchro-
nous with the data. The other RCxP/N clocks will be
frequency locked, but will have an arbitrary phase
relationship with the data.
Incidental errors occurring in the received data can
transform a normal data character into a K28.5 char-
acter. To prevent this occurrence from causing a
single channel from attempting word re-alignment,
possibly resulting in loss of channel lock, the S2065
implements a state machine which controls the syn-
chronization process when operating in the CHAN-
NEL LOCK mode.
Note that when operating in the CHANNEL LOCK
mode, the TCLK[B:D] inputs must be tied LOW. Fail-
ure to do this will result in improper operation of the
S2065.
Channel Lock Mode Synchronization
Incidental errors occurring in the received data can
transform a normal data character into a K28.5 char-
acter. To prevent this occurrence from making the
channel locking process unnecessarily vulnerable to
bit errors, the S2065 implements a channel lock
state machine for each channel with linkage between
channels to move to the final de-skewed state.
The Channel Lock state diagram is shown in Figure
8. The S2065 powers up in the “No Sync” state.
When in the “No Sync” state, each channel of the
S2065 is actively searching the received data stream
for the occurrence of a K28.5 and will align its de-
multiplexor to the character when detected, and will
enter the “Acquiring Sync” state. K28.5 will be re-
ported on each channel as 0-1-1 (err-eof-kflag).
When four or more consecutive K28.5 characters are
received on a given channel, the channel will enter
the “Re-sync” state as shown in Figure 8. "Re-Sync"
state status will not be reported as 1-1-1 until the
first valid data character has been received. If all
four channels are in the "Re-sync" state and each
has received a valid data character within the
deskew time of 5 bytes, then the S2065 will channel
lock by aligning the data output from each channel
such that the first valid data character for each chan-
nel is output simultaneously. The device will move to
the “In Sync” state and indicate channel lock status
by each channel as a 0-1-0. Note that “Re-sync” is
reported independently by each channel regardless
of the state of the other channels. However, “In
Sync” can only be reported when all four channels
are in the “In Sync” state and detect a valid data
character within the deskew window. The “In Sync”
state is reported for each as 0-1-0.
Once the S2065 has entered the “In Sync” state, it will
report status but will not alter the relative skew of the
output FIFOs. The S2065 will exit the “In Sync” state
and move to the “No Sync” state if one of the four
CRUs reports a loss of lock, if the 8B/10B decoder
observes four consecutive decoding errors, or if the
decoder error rate >50% in a block of 16 codewords.
The device can also be put in the “No Sync” state by
setting SOFD=Low, asserting RESET, or by momen-
tarily de-asserting CH_LOCK signal.
SOFD is used to reset the Channel Lock state ma-
chine and provides minimum disruption of the data
path.
When not in Channel Lock Mode, the linkage be-
tween the four state machines is broken and each
channel operates independently.
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S2065J 制造商:Littelfuse 功能描述:Thyristor Thyristor/Triac Type:SCR
S2065J_ 功能描述:SCR - Use 576-S2065J RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開(kāi)啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube
S2065JTP 功能描述:SCR SCR 200V 65A Iso RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開(kāi)啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube
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