參數(shù)資料
型號(hào)： S2067
廠商： Applied Micro Circuits Corp.
英文描述： Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器)
中文描述： 雙串行背板收發(fā)器/輸出（帶雙傳送接收串行的I / O的雙收發(fā)器雙一）
文件頁(yè)數(shù)： 1/28頁(yè)
文件大?。?/td> 306K
代理商： S2067
1
S2067
S2067
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision E
DEVICE
SPECIFICATION
FEATURES
Broad operating rate range
(0.77 GHz - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
Dual Transmitter incorporating phase-locked
loop (PLL) clock synthesis from low speed
reference
Dual Receiver PLL provides independent clock
and data recovery for each channel
Internally series terminated TTL outputs
On-chip 8B/10B Line encoding and decoding for
2 separate parallel 8 bit channels
(2x8) bit parallel TTL interface
Low-jitter serial PECL interface
Local Loopback
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 1.6 W Power dissipation
Compact 21mm x 21mm 156 TBGA package
Redundant high speed transmit and receive
serial interfaces
APPLICATIONS
High-speed data communications
Ethernet Backbones
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2067 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides two
separate transceivers which can be operated indi-
vidually for a data capacity of >2 Gbit/sec in each
direction. The S2067 provides dual transmit and re-
ceive serial I/O. The dual transmit and receive serial
I/O are useful for backbone applications in which re-
dundant optical or electrical links are required.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip dual
receive PLL is used for clock recovery and data re-
timing on the two independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Re-
dundant transmit and receive serial I/O are provided
to support applications with redundant switch fabrics
or line interfaces. Local loopback mode allows for
system diagnostics. The chip requires a 3.3V power
supply and dissipates 1.6 watts.
Figure 1 shows the use of the S2067 and S2068 in a
Gigabit Ethernet application. Figure 2 shows the use of
a S2067 in a serial backplane application. Figure 3
summarizes the input and output signals on the S2067.
Figures 4 and 5 show the transmit and receive block
diagrams, respectively.
Figure 1. Typical Dual Gigabit Ethernet Application
MAC
(ASIC)
DUAL
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
GE INTERFACE
SERIAL BP DRIVER
TO SERIAL BACKPLANE
S2068
S2067
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