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參數(shù)資料
| 型號： | S2067 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器) |
| 中文描述： | 雙串行背板收發(fā)器/輸出（帶雙傳送接收串行的I / O的雙收發(fā)器雙一） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 306K |
| 代理商： | S2067 |
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6
S2067
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision E
Figures 6 and 7 illustrate the broad range of transmit
data clocking options supported by the S2067.
Figure 6 demonstrates the flexibility afforded by the
S2067. A low jitter reference is provided directly to
the S2067 at either 1/10 or 1/20 the serial data rate.
This ensures minimum jitter in the synthesized clock
used for serial data transmission. A system clock out-
put at the parallel word rate, TCLKO, is derived from
the PLL and provided to the upstream circuit as a
system clock. This clock can be buffered as required
without concern about added delay. There is no
phase requirement placed upon TCLKO and TCLKx,
which is provided back to the S2067, other than that
they remain within
±
3ns of the phase relationship
established at reset.
The S2067 also supports the traditional REFCLK
(TBC) clocking found in Fibre Channel and Gigabit
Ethernet applications and is illustrated in Figure 7.
Half Rate Operation
TRANSMITTER DESCRIPTION
The transmitter section of the S2067 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Two channels are
provided with a variety of options regarding input
clocking and loopback. The transmitters can operate
in the range of 0.77 GHz to 1.3 GHz, 10 or 20 times
the reference clock frequency. The transmitter func-
tions are shown schematically in Figure 4.
Data Input
The S2067 has been designed to simplify the paral-
lel interface data transfer and provides the utmost in
flexibility regarding clocking of parallel data. Prior, or
less sophisticated, implementations of this function
have either forced the user to synchronize transmit
data to the reference clock or to provide the output
clock as a reference to the PLL, resulting in in-
creased jitter at the serial interface. The S2067 in-
corporates a unique input structure, which enables
the user to provide a “clean” reference source for the
PLL and to accept a separate external clock, which
is used exclusively to reliably clock data into the de-
vice.
The S2067 also provides a system clock output,
TCLKO, which is derived from the internal VCO. The
frequency of this output is constant at the parallel
word rate, 1/10 the serial data rate, regardless of
whether the reference is provided at 1/10 or 1/20 the
serial data rate. This clock can be used by upstream
circuitry as a system clock.
Data is input to each channel of the S2067 nominally
as a 10-bit wide word. This consists of 8-bits of user
data, KGEN, and SOF. An input FIFO and a clock
input, TCLKx, are provided for each channel of the
S2067. The S2067 can be configured to use either
the TCLKx (TCLK MODE) input or the REFCLK input
(REFCLK MODE). In TCLK or REFCLK mode, each
byte of data is clocked into its FIFO with the TCLKx
provided with each byte. A TTL clock (TCLKO) at the
parallel data rate is provided by the S2067 for use by
upstream circuitry. The TCLKO is derived from the
transmit VCO. Table 1 provides a summary of the
input modes for the S2067.
Operation in the TCLK MODE makes it easier for
users to meet the relatively narrow setup and hold
time window required by the parallel 10-bit interface.
The TCLK signal is used to clock the data into an
internal holding register and the S2067 synchronizes
its internal data flow to ensure stable operation. The
TCLK is not used as a reference to the VCO. This
facilitates the provision of a clean reference clock
resulting in minimum jitter on the serial output. The
TCLK must be frequency locked to REFCLK, but
may have an arbitrary but fixed phase relationship.
Adjustment of internal timing of the S2067 is per-
formed during reset. Once synchronized, the S2067
can tolerate up to
±
3ns of phase drift between TCLK
and REFCLK.
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
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Table 1. Input Modes
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