參數(shù)資料
型號(hào)： S2067
廠商： Applied Micro Circuits Corp.
英文描述： Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器)
中文描述： 雙串行背板收發(fā)器/輸出（帶雙傳送接收串行的I / O的雙收發(fā)器雙一）
文件頁數(shù)： 10/28頁
文件大?。?/td> 306K
代理商： S2067
10
S2067
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision E
Clock Recovery Function
Clock recovery is performed on the input data
stream for each channel of the S2067. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the VCO to lock to the refer-
ence clock. This allows the VCO to maintain the cor-
rect frequency in the absence of data.
The ‘lock to reference’ frequency criteria insure that
the S2067 will respond to variations in the serial data
input frequency (compared to the reference fre-
quency). The new Lock State is dependent upon the
current lock state, as shown in Table 6.
The run-length criteria insure that the S2067 will re-
spond appropriately and quickly to a loss of signal.
The run-length checker flags a condition of consecu-
tive ones or zeros across 12 parallel words. Thus
119 or less consecutive ones or zeros does not
cause signal loss, 129 or more causes signal loss,
and 120 - 128 may or may not, depending on how
the data aligns across byte boundaries.
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Table 6. Lock to Reference Frequency Criteria
If both the off-frequency detect circuitry test and the
run-length test are satisfied, the CRU will attempt to
lock to the incoming data. When lock is achieved,
LOCK-DET is asserted on the ERR, EOF, and
KFLAG status lines. It is possible for the run length
test to be satisfied due to noise on the inputs, even if
no signal is present. In this case the lock detect sta-
tus may periodically assert as the VCO frequency
approaches that of the REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RCxP/N outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
When operating in TCLK mode, both PLL lock status
are indicated by a 1-0-1 on the ERR, EOF, and
KFLAG outputs, respectively.
Reference Clock Input
The reference clock must be provided from a low jitter
clock source. The frequency of the received data
stream (divided-by-10 or 20) must be within 200 ppm
of the reference clock to ensure reliable locking of the
receiver PLL. A single reference clock is provided to
both the transmitter and the receiver of the S2067.
Serial to Parallel Conversion
Once bit synchronization has been attained by the
S2067 CRU, the S2067 must synchronize to the 10
bit word boundary. Word synchronization in the
S2067 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2067 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2067 will detect and align to a K28.5
anywhere in the data stream. For TCLK or REFCLK
mode operation, the presence of a K28.5 is indicated
for each channel by the assertion of the EOFx sig-
nal. Table 8 details the function of the EOF, KFLAG,
and ERR pins in status reporting.
As indicated in Table 8, a 1-0-1 on the ERR, EOF,
and KFLAG signals on any channel is indicative of
CRU lock failure.
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