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參數(shù)資料
| 型號： | S2073 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Five Port Bypass and Repeater for FC-AL(用于FC-AL的五端口旁路電路和中繼器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 159K |
| 代理商： | S2073 |
1
FIVE PORT BYPASS AND REPEATER FOR FC-AL
S2073
S2073
February 9, 2000 / Revision D
FEATURES
ANSI X3T11 Fibre Channel Compliant
Monolithic Clock Recovery Unit
– Retimes & Buffers Received Data
– Jitter Peaking < 0.1 dB
Lock Detect Function
– Frequency Detection
Five Port Bypass Circuits
Suitable for both Coaxial and Optical Link
Low Power Operation 0.93 W Typical
106.25 or 53.125 MHz Reference Clock
Compact 10 mm x 10 mm 64 Pin
PQFP Package
3.3 V Supply
Micropower Bipolar Technology
APPLICATIONS
FC-AL Nodes
RAID
JBOD
SAN
GENERAL DESCRIPTION
The Five Port Bypass and Repeater for FC-AL Cir-
cuit is used in full-speed (1.0625 Gb/s) Disk Arrays.
It contains a monolithic Clock Recovery Unit (CRU),
a lock detect feature and five port bypass circuits.
The S2073 may be used to implement a single chip
Figure 1. S2073 Functional Block Diagram
DEVICE
SPECIFICATION
Arbitrated Loop Port Bypass Retiming Node. The
S2073 performs the function of five port bypass cir-
cuits followed by a Clock and Data Retimer (CDR).
The CDR retimes incoming serial data, detects
whether a valid signal is present and outputs a low
jitter serial data stream.
FUNCTIONAL DESCRIPTION
The S2073 functional block diagram is shown in Fig-
ure 1. The S2073 performs two functions. The first
function is a five Port Bypass Circuit (PBC) for nodes
in a FC-AL system. The low jitter accumulation of the
port bypass path is essential in these systems. The
second function is to restore signal quality in RAID
drives using the FC-AL link configuration. The S2073
clock and data recovery PLL provides low jitter
transfer peaking and high jitter tolerance. In addition,
the lock detect circuit monitors the incoming signals
for frequency, which is useful for link performance
monitoring and detection of channel present.
Jitter Performance
Input jitter tolerance is defined as the amplitude of
frequency dependent, random and deterministic jitter
that causes the clock recovery PLL to violate the
BER specifications.
The S2073 complies with the minimum jitter toler-
ance requirements proposed by the Fibre Channel
jitter working group when used with differential in-
puts and outputs as shown in Figure 2. In addition,
the S2073 is designed for minimum jitter generation
and jitter transfer specifications. This allows the opti-
mum system design for arbitrated loop architectures.
0
1
0
1
0
1
0
1
DDO0 DDI0
EN0
DDO1
DDI1
EN1
DDO2
DDI2
EN2
DDO3 DDI3
EN3
0
1
DDO4
DDI4
EN4
IN
CDR
OUTP/N
LOCKDET
B
R
L
R
L
L
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