- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374647 > S2074 (APPLIEDMICRO INC) Six Port Bypass and Repeater for FC-AL(用于FC-AL的六端口旁路電路和中繼器) PDF資料下載
參數(shù)資料
| 型號(hào)： | S2074 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Six Port Bypass and Repeater for FC-AL(用于FC-AL的六端口旁路電路和中繼器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | S2074 |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
1
SIX PORT BYPASS AND REPEATER FOR FC-AL
S2074
S2074
February 9, 2000 / Revision D
FEATURES
ANSI X3T11 Fibre Channel Compliant
Monolithic Clock Recovery Unit
– Retimes & Buffers Received Data
– Jitter Peaking < 0.1 dB
Lock Detect Function
– Frequency Detection
Six Port Bypass Circuits
Suitable for both Coaxial and Optical Link
Low Power Operation 0.98 W Typical
106.25 or 53.125 MHz Reference Clock
Compact 14 mm x 14 mm 64 Pin
PQFP Package
3.3 V Supply
Micropower Bipolar Technology
APPLICATIONS
FC-AL Nodes
RAID
JBOD
SAN
GENERAL DESCRIPTION
The Six Port Bypass and Repeater for FC-AL Circuit
is used in full-speed (1.0625 Gb/s) Disk Arrays. It
contains a monolithic Clock Recovery Unit (CRU), a
lock detect feature and six port bypass circuits. The
S2074 may be used to implement a single chip Arbi-
trated Loop Port Bypass Retiming Node. The S2074
Figure 1. S2074 Functional Block Diagram
DEVICE
SPECIFICATION
performs the function of six port bypass circuits fol-
lowed by a Clock and Data Retimer (CDR). The
CDR retimes incoming serial data, detects whether a
valid signal is present and outputs a low jitter serial
data stream.
FUNCTIONAL DESCRIPTION
The S2074 Functional Block Diagram is shown in
Figure 1. The S2074 performs two functions. The
first function is a six Port Bypass Circuit (PBC) for
nodes in a FC-AL system. The low jitter accumula-
tion of the port bypass path is essential in these
systems. The second function is to restore signal
quality in RAID drives using the FC-AL link configu-
ration. The S2074 clock and data recovery PLL pro-
vides low jitter transfer peaking and the high jitter
tolerance. In addition, the lock detect circuit monitors
the incoming signals for frequency, which is useful
for link performance monitoring and detection of
channel present.
Jitter Performance
Input jitter tolerance is defined as the amplitude of
frequency dependent, random and deterministic jitter
that causes the clock recovery PLL to violate the
BER specifications.
The S2074 complies with the minimum jitter toler-
ance requirements proposed by the Fibre Channel
jitter working group when used with differential in-
puts and outputs as shown in Figure 2. In addition,
the S2074 is designed for minimum jitter generation
and jitter transfer specifications. This allows the opti-
mum system design for arbitrated loop architectures.
0
1
0
1
0
1
0
1
DDO0 DDI0
EN0
DDO1
DDI1
EN1
DDO2
DDI2
EN2
DDO3 DDI3
EN3
0
1
DDO4
DDI4
EN4
0
1
DDO5 DDI5
EN5
IN
CDR
OUTP/N
LOCKDET
B
R
L
R
L
L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2075 | Fibre Channel Bit Stream Monitor with Repeater(帶中繼器的光纖位流監(jiān)視器) |
| S2076 | Quad Fibre Channel Transceiver(四光纖通道收發(fā)器) |
| S2078 | Dual Fibre Channel Transceiver(雙光纖通道收發(fā)器) |
| S2080 | 34×34 3.2 Gbit/s Differential Crosspoint Switch(高達(dá)3.2 Gbit/s數(shù)據(jù)傳送速率的34×34差分交叉開關(guān)) |
| S208T01 | Low Profile Type Solid State Relays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2079 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Drivers for GaAs FET Switches and Digital Attenuators |
| S2079B1LF | 制造商:BOTHHAND 制造商全稱:Bothhand USA, LP. 功能描述:ISDN S-INTERFACE DUAL TRANSFORMER MODULES SMLL SMT PACKAGE 23.5×12.3×9mm |
| S207R | 制造商:MINMAX 制造商全稱:Minmax Technology Co., Ltd. 功能描述:2W, Low Cost DIP, Single & Dual Output DC/DC Converters |
| S-208 | 制造商:SCANBE/VERO 功能描述: |
| S2080 | 制造商:Tyan 功能描述:MB;ATX;S370;PIIIT;SDRAM;SINGLE 制造商:Microsemi Corporation 功能描述:800V 16A 2PIN DO-203AA - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。