參數(shù)資料
型號(hào)： S2067
廠商： Applied Micro Circuits Corp.
英文描述： Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器)
中文描述： 雙串行背板收發(fā)器/輸出（帶雙傳送接收串行的I / O的雙收發(fā)器雙一）
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 306K
代理商： S2067
9
S2067
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision E
Frequency Synthesizer (PLL)
The S2067 synthesizes a serial transmit clock from
the reference signal provided. The S2067 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-
detect output is NOT provided.
Reference Clock Input
The reference clock input must be supplied with a low-
jitter clock source. All reference clocks in a system
must be within 200 ppm of each other to ensure that
the clock recovery units can lock to the serial data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL
= 1. Note that in both
cases the frequency of the parallel word rate output,
TCLKO, is constant at 1/10 the serial data rate. See
Table 5.
Serial Data Outputs
Two high-speed differential outputs are provided for
each channel. This enables each channel to drive a
primary and secondary switch fabric for backplane
applications in which redundancy is required to
achieve higher reliability or hot-swappability. The pri-
mary and secondary high speed outputs remain ac-
tive except when the Loopback Mode is enabled.
Each high speed output should be provided with a
resistor to VSS (Gnd) near the device. A value of
4.5K
provides optimal performance with minimum
impact on power dissipation. The resistance may be
as low as 450
, but will dissipate additional power
with no substantive performance improvement. Out-
puts are designed to perform optimally when AC-
coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. The DIN FIFO is
automatically reset upon power up immediately after
the DIN PLL obtains stable frequency lock. If the
circuit has not reached steady state timing at this
point, then the user must initialize by asserting the
RESET signal. The TCLKO output will operate nor-
mally even when RESET is asserted and is available
for use as an upstream clock source.
RECEIVER DESCRIPTION
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 5.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2067 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the decoded data on its parallel outputs.
Data Input
Two differential receivers are provided for each chan-
nel of the S2067. This supports switching between
redundant switch fabrics for serial backplane applica-
tions. Each channel has a loopback mode in which
the serial data from the transmitter replaces serial in-
put data. The loopback function for both channels is
controlled by the loopback enable signal, LPEN.
The high speed serial inputs to the S2067 are inter-
nally biased to VDD-1.3V to simplify AC-coupling of
the differential inputs and allow differential termina-
tion with a single resistor.
Table 5. Operating Rates
E
T
A
R
L
E
S
K
L
C
K
c
L
n
C
e
u
F
E
q
e
R
r
y
F
t
u
p
t
u
O
l
e
S
e
R
O
n
K
e
L
u
C
q
T
e
r
y
c
F
0
0
0
1
R
D
S
z
H
G
3
–
7
7
0
1
R
D
S
0
1
0
2
R
D
S
z
H
G
3
–
7
7
0
1
R
D
S
1
0
0
1
R
D
S
z
H
G
5
6
3
0
1
R
D
S
1
1
0
2
R
D
S
z
H
G
5
6
3
0
1
R
D
S
Note: SDR = Serial Data Rate.
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