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參數(shù)資料
| 型號： | S2067 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器) |
| 中文描述： | 雙串行背板收發(fā)器/輸出（帶雙傳送接收串行的I / O的雙收發(fā)器雙一） |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 306K |
| 代理商： | S2067 |
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11
S2067
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision E
8B/10B Decoding
After performing serial-to-parallel conversion, the
S2067 provides 8B/10B decoding of the data. The
received 10-bit codeword is decoded to recover the
original 8-bit data. The decoder also checks for er-
rors and flags, either invalid codeword errors or run-
ning disparity errors by assertion of the ERRx signal.
Error type is determined by examining the EOF out-
put in accordance with Table 8. When more than one
reportable condition occurs simultaneously, reporting
is in accordance with the rank assigned by Table 8.
Data Output
Data is output on the DOUT[0:7] outputs. K-charac-
ters are flagged using the KFLAG signal. The EOF
(with KFLAG) is used to indicate the reception of a
valid K28.5 character. Invalid codewords and decod-
ing errors are indicated on the ERR output. KFLAG,
EOF, and ERR are buffered with the data in the
FIFO to ensure that all outputs are synchronized at
the S2067 outputs. Errors are reported indepen-
dently for each channel in TCLK or REFCLK mode
operation.
The S2067 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported. When
CMODE is HIGH, a complementary TTL clock at the
data rate is provided on the RCxP/N outputs. Data
should be clocked on the rising edge of RCxP. When
CMODE is LOW, a complementary TTL clock at 1/2
the data rate is provided. Data should be latched on
the rising edge of RCxP and the rising edge of
RCxN.
The S2067 will operate properly when multiple K28.5
characters are received. Byte alignment is achieved
after the first K28.5 is received. The RCxP/N clock
operates without glitches or loss of cycles.
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Table 7. Output Clock Modes
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Table 8. Error and Status Reporting
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