參數(shù)資料
型號: S2068
廠商: Applied Micro Circuits Corp.
英文描述: Dual GigaBit Ethernet Transceiver(雙千兆位以太網(wǎng)收發(fā)器)
中文描述: 雙千兆以太網(wǎng)收發(fā)器(雙千兆位以太網(wǎng)收發(fā)器)
文件頁數(shù): 1/24頁
文件大?。?/td> 277K
代理商: S2068
1
S2068
S2068
DUAL GIGABIT ETHERNET TRANSCEIVER
October 13, 2000 / Revision D
DEVICE
SPECIFICATION
FEATURES
Functionally compliant with IEEE 802.3z Gigabit
Ethernet Applications
1250 MHz (Gigabit Ethernet) operating rate
– Half rate operation
Dual Transmitter incorporating phase-locked
loop (PLL) clock synthesis from low speed
reference
Dual Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
Low-jitter serial PECL interface
Local Loopback
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 1.37W power dissipation
Compact 21mm x 21mm 156 TBGA package
APPLICATIONS
High-speed data communications
Ethernet Backbones
Multi-port Gigabit Ethernet Cards
Switched networks
Data broadcast environments
GENERAL DESCRIPTION
The S2068 dual transmitter and receiver chip is de-
signed to provide two channels of high-speed serial
data transmission over fiber optic or copper interfaces
conforming to the requirements of the IEEE 802.3z
Gigabit Ethernet specification. The chip runs at
1250.0 Mbps serial data rate with an associated
10-bit parallel data word. The chip provides two sepa-
rate receive PLLs which can be operated asynchro-
nously at slightly different frequencies.
Each bi-directional channel provides parallel to serial
and serial-to-parallel conversion, clock generation
and recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip dual receive PLL is used for
clock recovery and data re-timing on the two inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces and pro-
vide excellent signal integrity. Local loopback mode
allows for system diagnostics. The chip requires a
3.3V power supply and dissipates 1.37 watts.
Figure 1 shows the use of the S2062 and S2068 in a
Gigabit Ethernet application. Figure 2 summarizes
the input/output signals of the device. Figures 3 and
4 show the transmit and receive block diagrams, re-
spectively.
Figure 1. Typical Dual Gigabit Ethernet Application
MAC
(ASIC)
S2062
DUAL
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
TO SERIAL
BACKPLANE
S2068
GE INTERFACE
SERIAL BP DRIVER
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