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參數(shù)資料
| 型號： | S2065 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器) |
| 中文描述： | 四串行設備，配有雙背板的I / O（帶雙傳送接收串行的I / O的四收發(fā)器） |
| 文件頁數(shù)： | 11/37頁 |
| 文件大?。?/td> | 381K |
| 代理商： | S2065 |
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11
S2065
QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision G
RECEIVER DESCRIPTION
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 5.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2065 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the decoded data on its parallel outputs.
The S2065 has the ability to operate with all four
channels locked together (CHANNEL LOCK mode).
The channel lock process and status reporting is de-
scribed later in this document.
Data Input
Two differential receivers are provided for each chan-
nel of the S2065. This supports switching between
redundant switch fabrics for serial backplane applica-
tions. Each channel has a loopback mode in which
the serial data from the transmitter replaces serial in-
put data. The loopback function for all four channels is
controlled by the loopback enable signal, LPEN.
The high speed serial inputs to the S2065 are inter-
nally biased to VDD-1.3V to simplify AC-coupling of
the differential inputs and allow differential termina-
tion with a single resistor.
Clock Recovery Function
Clock recovery is performed on the input data
stream for each channel of the S2065. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the VCO to lock to the refer-
ence clock. This allows the VCO to maintain the cor-
rect frequency in the absence of data.
The ‘lock to reference’ frequency criteria insure that
the S2065 will respond to variations in the serial data
input frequency (compared to the reference fre-
quency). The new Lock State is dependent upon the
current lock state, as shown in Table 6.
The run-length criteria insure that the S2065 will re-
spond appropriately and quickly to a loss of signal.
The run-length checker flags a condition of consecu-
tive ones or zeros across 12 parallel words. Thus
119 or less consecutive ones or zeros does not
cause signal loss, 129 or more causes signal loss,
and 120 - 128 may or may not, depending on how
the data aligns across byte boundaries.
If both the off-frequency detect circuitry test and the
run-length test are satisfied, the CRU will attempt to
lock to the incoming data. When lock is achieved,
LOCK-DET is asserted on the ERR, EOF, and
KFLAG status lines. It is possible for the run length
test to be satisfied due to noise on the inputs, even if
no signal is present. In this case the lock detect sta-
tus may periodically assert as the VCO frequency
approaches that of the REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RCxP/N outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
When operating in independent mode, all four PLL
lock status is indicated by a 1-0-1 on the ERR, EOF,
and KFLAG outputs, respectively. When operating in
the CHANNEL LOCK mode, PLL locking of all four
channels must be accomplished before byte-skewing
is achieved and “In Sync” status is indicated on the
ERR, EOF, and KFLAG outputs.
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Table 6. Lock to Reference Frequency Criteria
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相關代理商/技術參數(shù) |
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| S2065A | 制造商:AppliedMicro 功能描述:Backplane Transceiver 208-Pin TBGA |
| S2065J | 功能描述:SCR 65A 200V RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
| S2065J | 制造商:Littelfuse 功能描述:Thyristor Thyristor/Triac Type:SCR |
| S2065J_ | 功能描述:SCR - Use 576-S2065J RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
| S2065JTP | 功能描述:SCR SCR 200V 65A Iso RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
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