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參數(shù)資料
| 型號： | S2065 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器) |
| 中文描述： | 四串行設(shè)備，配有雙背板的I / O（帶雙傳送接收串行的I / O的四收發(fā)器） |
| 文件頁數(shù)： | 10/37頁 |
| 文件大?。?/td> | 381K |
| 代理商： | S2065 |
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10
S2065
QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O
October 13, 2000 / Revision G
Frequency Synthesizer (PLL)
The S2065 synthesizes a serial transmit clock from
the reference signal provided. The S2065 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-
detect output is NOT provided.
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to ensure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL
= 1. Note that in both
cases the frequency of the parallel word rate output,
TCLKO, is constant at 1/10 the serial data rate.
Serial Data Outputs
Two high-speed differential outputs are provided for
each channel. This enables each channel to drive a
primary and secondary switch fabric for backplane
applications in which redundancy is required to
achieve higher reliability or hot-swappability. The pri-
mary and secondary high speed outputs remain ac-
tive except when the Loopback Mode is enabled.
Each high speed output should be provided with a
resistor to VSS (Gnd) near the device. A value of 4.5K
provides optimal performance with minimum impact
on power dissipation. The resistance may be as low
as 450
, but will dissipate additional power with no
substantive performance improvement. Outputs are
designed to perform optimally when AC-coupled.
When operating in the CHANNEL LOCK mode, the
user must ensure that the path length of the four high
speed serial data signals are matched to within 50 se-
rial bit times of delay. Failure to meet this requirement
may result in bit errors in the received data or in byte
misalignment. In addition to path length induced tim-
ing skew, the S2065 can tolerate up to
±
3 ns of
phase drift between channels after deskewing the
outputs.
Test Functions
The S2065 can be configured for factory test to aid
in functional testing of the device. When in the test
mode, the internal transmit and receive voltage-con-
trolled oscillator (VCO) is bypassed and the refer-
ence clock substituted. This allows full functional
testing of the digital portion of the chip or bypassing
the internal synthesized clock with an external clock
source. (See the section Other Operating Modes.)
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. The DIN FIFO is
automatically reset upon power up immediately after
the DIN PLL obtains stable frequency lock. If the
circuit has not reached steady state timing at this
point, then the user must initialize by asserting the
RESET signal. The TCLKO output will operate nor-
mally even when RESET is asserted and is available
for use as an upstream clock source.
Table 5. Operating Rates
E
T
A
R
L
E
S
K
L
C
K
c
L
n
C
e
u
F
E
q
e
R
r
y
F
t
u
p
t
u
O
l
e
S
e
R
O
n
K
e
L
u
C
q
T
e
r
y
c
F
0
0
0
1
R
D
S
z
H
G
3
–
7
7
0
1
R
D
S
0
1
0
2
R
D
S
z
H
G
3
–
7
7
0
1
R
D
S
1
0
0
1
R
D
S
z
H
G
5
6
3
0
1
R
D
S
1
1
0
2
R
D
S
z
H
G
5
6
3
0
1
R
D
S
Note: SDR = Serial Data Rate.
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