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| 型號(hào)： | QT0081411TUE |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 60/62頁 |
| 文件大?。?/td> | 268K |
| 代理商： | QT0081411TUE |
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IRQ Driveback
Page 50
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
There is a convention for assignment of otherwise unusable
IRQs:
IRQ2 generates an SMI#. Note that the sense of IRQ2 is
still active high. In this way, devices that use IRQ drive-
back can generate SMI# simply by routing their normal
interrupt to IRQ2 without needing to change the polarity of
the interrupt generation logic.
IRQ13 generates an NMI. This feature allows PCI-to-ISA
bridges such as the 82C825 chip to return the CHCK# sig-
nal from the ISA bus across the PCI bus. The sense of
IRQ13 is active high.
Table A-2 illustrates the format of the optional second data
phase of the IRQ driveback cycle. This phase is presently
reserved for returning the PCI interrupts and ACPI Events. If
the device needs to send back level-model interrupts, it
bursts the information on the PCI clock following data phase
one. The IRQ driveback address automatically increments to
(base +4) per PCI requirements. It is also allowable for
devices to drive back only phase 2, by directly accessing the
(base +4) address.
Table A-2
Information Provided on a Optional Data Phase 2 of IRQ Driveback Cycle
A.2
The IRQs driven back in data phase 1 are interpreted as
edge-mode interrupts, as expected for AT compatibility. The
AD[15:0] signals are interpreted as active when high (1); the
Enable (EN#) signals AD[31:16] are active when low (0).
Edge vs Level Mode, IRQ Polarity
In optional data phase 2, the PCIRQ0-3 bits are interpreted
as level-mode interrupts by the host hardware. As with data
phase 1, the controls indicated by AD[15:0] are interpreted as
active when
high
; the Enable (EN#) controls on AD[31:16]
are active when
low
. Note that PCI signals INTA-D# are
active low by definition.
A.3
Host Handling of IRQ Driveback
Information
The host chipset must handle the IRQ driveback information
differently depending on whether the selected interrupt is
sharable or not. Generally the ISA IRQ lines need no special
consideration.
However, the INTA-D# lines can be shared by multiple
devices on the PCI bus. Thus, one device could perform an
IRQ driveback to set the INTx# line active for its purposes,
while another device could follow immediately by setting the
same INTx# line inactive. Therefore, the host is required to
implement a counter in this case, so that it considers the line
inactive only after it has received the same number of active-
going drivebacks as it has inactive-going drivebacks.
A three-bit counter can be considered sufficient to handle the
situation, since this would allow up to seven devices to chain
to the same interrupt. It is unlikely that system requirements
would exceed this number given the latency penalty incurred.
Low
Word
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
ACPI3
ACPI2
ACPI1
ACPI0
PCIRQ
3
PCIRQ
2
PCIRQ
1
PCIRQ
0
High
Word
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
EN
ACPI3#
EN
ACPI2#
EN
ACPI1#
EN
ACPI0#
ENP3#
ENP2#
ENP1#
ENP0#
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