
82C814
Page 38
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
PCICFG 85h
Window 0 Stop Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 86h
Window 0 Stop Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 87h
Window 0 Stop Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 88h
Window 0 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
Window 0 Mask Bits:
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space. 
-
Setting any bit to a 1 masks out the comparison on this bit. 
-
The register should be written to 0 to decode the entire address. 
-
Bits [1:0] are always 11 (masked).
RO:
Always returns 1.
PCICFG 89h
Window 0 Mask Register - Byte 1: Mask Bits [15:8]
Default = 00h
PCICFG 8Ah
Window 0 Mask Register - Byte 2: Mask Bits [23:16]
Default = 00h
PCICFG 8Bh
Window 0 Control Register
Default = 48h
Window points 
to ISA bus:
0 = No
1 = Yes
Reads are 
prefetchable:
0 = No
1 = Yes
Set to 0 for I/O 
window
Writes can be 
posted:
0 = No
1 = Yes
Set to 0 for I/O 
window
Reserved
Cycle qualifier:
0 = I/O
1 = Memory 
(Default)
Window 0 
Trap/SMI#:
0 = Disable
1 = Enable
Reserved
PCICFG 8Ch-8Fh
Reserved
Default = 00h
PCICFG 90h
Window 1 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 1 Start Address Bits:
-
Register bits [31:0] indicate the start address for Window 1. 
-
The selection between memory or I/O, as well as other feature selections, are made through the 
Window 1 Control Register.
RO:
Always 
returns 0
If memory: 
reads 0. 
If I/O: Decoding 
0 = 16-bit 
AD[31:16] = 0 
1 = 32-bit
PCICFG 91h
Window 1 Start Address Register - Byte 1: Address Bits [15:8]
Default = FFh
PCICFG 92h
Window 1 Start Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG 93h
Window 1 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
PCICFG 94h
Window 1 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 1 Stop Address Bits:
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows. 
RO: 
Always returns 0
PCICFG 95h
Window 1 Stop Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 96h
Window 1 Stop Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 97h
Window 1 Stop Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 98h
Window 1 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
Table 5-6
Docking Station Window Registers - PCICFG 80h-EFh  (cont.)
7
6
5
4
3
2
1
0