參數(shù)資料
型號(hào)： QT0081411TUE
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 41/62頁(yè)
文件大?。?/td> 268K
代理商： QT0081411TUE
82C814
912-3000-047
Revision: 1.0
Page 31
January 08, 1998
OPTi
5.3
The 82C814 defines many special functions that require
enabling and monitoring through a dedicated register set.
The 82C814-specific registers at PCICFG 50h-5Fh remain
set to their programmed values even after a device is
removed from the slot. Also, PCICFG 50h is common to both
slot interfaces (i.e. changing the bit in one PCI register set
changes it in the other).
82C814-Specific Register Group
The following subsections discuss some of the special func-
tions located in the 82C814-Specific Register Group.
5.3.1
PCICFG 50h[2] selects whether the CLKRUN# signal to the
host will toggle. Normally it will be set for automatic operation.
In this mode, the 82C814 logic asserts CLKRUN# only when
it wants bus ownership for master cycles, or when it has an
interrupt it must send to the host. At all other times, it leaves
CLKRUN# tristated and depends on the current PCI bus
master to assert CLKRUN# and keep the clock running.
CLKRUN#
5.3.2
Slot Buffer Enable, Slew Rate, and
Threshold Control
PCICFG 51h[2:0] are automatically updated by the card
insertion state machine according to whether a 5.0V or 3.3V
dock has been detected using CD1-2# and VS1-2. Once the
card has been inserted and detected, and the interface auto-
matically set appropriately, software can still override the
automatic settings by reading and then writing PCICFG
51h[2:0] as desired.
5.3.3
Dual ISA buses are possible with the 82C814 chip used in
conjunction with the OPTi PCI-ISA Bridge chips. This feature
depends on the ISA Windows feature of the 82C814 chip,
which allows cycles destined for the remote docking ISA bus
to be claimed with positive decoding from the primary PCI
bus and then retried. If the cycle turns out not to be destined
for the docking ISA bus, the 82C814 chip ignores the next
retry so that the cycle will be claimed using subtractive
decode by the host chipset.
Dual ISA Buses
The FireStar chip provides an additional feature that allows
positive decode of cycles to known local ISA devices. This
feature would conflict with the positive decode used by the
82C814 chip. Therefore, the 82C814 chip has the option of
decoding on the slow clock instead of on the medium clock.
This feature is enabled by writing PCICFG 5Eh[7] = 1.
When the feature is selected, the 82C814 logic will monitor
the DEVSEL# line to determine whether FireStar (or anyone
else) has claimed the cycle by fast or medium decode. Only if
DEVSEL# remains high through the medium decode clock
will the 82C814 chip claim the cycle.
The slow decode feature works only for windows enabled as
ISA windows. Other windows will continue to use a medium
decode.
Compaq SIRQ
HALT mode
request:
0 = Active
1 = Halt
Compaq SIRQ
QUIET mode
request:
0 = Continuous
1 = Quiet
Reserved
Compaq SIRQ
data frame
slots. Change
only when the
Serial IRQ logic
is disabled or in
Halt state.
0 = 17 slots
1 = 21 slots
Compaq SIRQ Start frame width
in PCI clocks. Change this setting
only when Serial IRQ is disabled
or in Halt state.
00 = 4 PCI clocks
01 = 6 PCI clocks
10 = 8 PCI clocks
11 = Reserved
Reserved
Compaq SIRQ
(Compaq Serial
IRQ scheme):
0 = Disable
1 = Enable
PCICFG 4Fh
Serial IRQ Control Register 2 And External Arbiter Enable
Default = 00h
Compaq SIRQ
in HALT state
(RO)
0 = No
1 = Yes
Compaq SIRQ
in QUIET state
(RO)
0 = No
1 = Yes
Reserved
External Arbiter
on secondary
PCI:
0 = Disable
1 = Enable
Table 5-1
Base Register Group - PCICFG 00h-4Fh (cont.)
7
6
5
4
3
2
1
0
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