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| 型號(hào)： | QT0081411TUE |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 44/62頁 |
| 文件大小： | 268K |
| 代理商： | QT0081411TUE |
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82C814
Page 34
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
5.4
The CardBus-style control and status register group is acces-
sible through two different means. It is always accessible as
part of the PCI configuration space at the indexes shown in
Table 5-4. In addition, when the CardBus register base
address at PCICFG 14h is written to any value other than
zero, these same registers can be accessed through the sys-
tem memory space selected (see Table 5-3).
CardBus Register Group
Note that when accessing these registers in PCI memory
space, they start from an offset of 00h, not 60h, from the reg-
ister base address programmed.
5.4.1
PCICFG 70h[6:4] set the external VCC5 and VCC3 pin lev-
els. Because only these two pins are available on the 82C814
interface, the system must be designed to interpret these sig-
nals properly and select the correct voltage for the applica-
tion.
Power Control
Table 5-3
CardBus Register Set in System
Memory
PCICFG 5Eh
Primary Retry Limit Register
Default = 00h
Slow decode for
ISA windows:
0 = Disable
1 = Enable
Prefetch on
upstream
transactions:
0 = Disable
1 = Enable
Posted writes
on upstream
transactions:
0 = Disable
1 = Enable
Core voltage:
0 = 3.3V
1 = 5.0V
Retry count
readback
control:
0 = Write post-
ing retries
on second-
ary
1 = Retries on
primary
Retry Limit:
These bits relate to the number of times that the
82C814, as a slave, will retry accesses on the pri-
mary. If this limit is exceeded, the 82C814 gener-
ates SERR# to the host.
000=2
8
100=2
16
001=2
10
101=2
20
010=2
12
110=2
24
011=2
14
111= Infinite retries (Default)
PCICFG 5Fh
-
This register returns the number of retry attempts made.
-
More than 256 retries are indicated by FFh.
-
Used for diagnostic purposes. Read-only.
-
Separate counts are maintained for primary and secondary. Bit 5Eh[3] selects the count being read back.
82C814 Retry Count Readback Register (RO)
Default = 00h
Write-Only:
This register is also writable, for factory diagnostic purposes only.
Status Change Initialization
When PCICFG
0 = Old scheme
1 = New
1 = Variation
51h[3]=1
0 = Automatic
Mode
1 = Sync mode
PCI Retry Test
0 = Disable
1 = Enable
Prototype test
mode:
0 = Disable
1 = Enable
Force FIFO
clear
Retry test
times:
0 = Normal
1 = Quick*
Power-up and
detect timer:
0 = Normal
1 = Quick
0 = Original
*
Quick Mode will not function unless PCICFG 5Eh[2:0] is zero.
Table 5-2
Specific Register Group - PCICFG 50h-5Fh (cont.)
7
6
5
4
3
2
1
0
CardBus Base
Address plus:
Name
000h
004h
008h
00Ch
010h
014-7FFh
Socket Event Register
Socket Mask Register
Socket Present State Register
Force Event Register
Control Register
Reserved
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