參數(shù)資料
型號(hào)： QT0081411TUE
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 50/62頁(yè)
文件大?。?/td> 268K
代理商： QT0081411TUE
82C814
Page 40
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
PCICFG ABh
Window 2 Control Register
Default = 00h
Window points
to ISA bus:
0 = No
1 = Yes
Reads are
prefetchable:
0 = No
1 = Yes
Set to 0 for I/O
window
Writes can be
posted:
0 = No
1 = Yes
Set to 0 for I/O
window
Reserved
Cycle
qualifier:
0 = I/O (Default)
1 = Memory
Window 2
Trap/SMI#:
0 = Disable
1 = Enable
Reserved
PCICFG ACh-AFh
Reserved
Default = 00h
PCICFG B0h
Window 3 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 3 Address Bits:
-
Register bits [31:0] indicate the start address for Window 3.
-
The selection between memory or I/O, as well as other feature selections, are made through the
Window 3 Control Register.
RO:
Always
returns 0
If memory:
reads 0.
If I/O: Decoding
0 = 16-bit
AD[31:16] = 0
1 = 32-bit
PCICFG B1h
Window 3 Start Address Register - Byte 1: Address Bits [15:8]
Default = FFh
PCICFG B2h
Window 3 Start Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG B3h
Window 3 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
PCICFG B4h
Window 3 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 3 Stop Address Bits:
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
RO:
Always returns 0
PCICFG B5h
Window 3 Stop Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG B6h
Window 3 Stop Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG B7h
Window 3 Stop Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG B8h
Window 3 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
Window 3 Mask Bits:
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space.
-
Setting any bit to a 1 masks out the comparison on this bit.
-
The register should be written to 0 to decode the entire address.
-
Bits [1:0] are always 11 (masked).
-
Bit 23 is always 0
RO:
Always returns 1.
PCICFG B9h
Window 3 Mask Register - Byte 1: Mask Bits [15:8]
Default = 00h
PCICFG BAh
Window 3 Mask Register - Byte 2: Mask Bits [23:16]
Default = 00h
Bit 23
Reserved
Bits [22:16]
PCICFG BBh
Window 3 Control Register
Default = 00h
Table 5-6
Docking Station Window Registers - PCICFG 80h-EFh (cont.)
7
6
5
4
3
2
1
0
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