參數(shù)資料
型號(hào)： QT0081411TUE
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 33/62頁(yè)
文件大?。?/td> 268K
代理商： QT0081411TUE
82C814
912-3000-047
Revision: 1.0
Page 23
January 08, 1998
OPTi
5.0
82C814 Register Set
The 82C814 Docking Controller chip provides a single group
of programming registers, PCI-to-CardBus Bridge 0 Register
Group, accessed through a PCI Configuration Cycle to Func-
tion 0 of the chip. Consists of CardBus Controller Base Reg-
ister Group at PCICFG 00h-4Fh, 82C814-specific registers at
50h-5Fh, CardBus Control and Status Register Group at 60h-
7Fh, and Docking Station Window Register Group at 80h-
FFh. Note that the CardBus Control and Status Register
Group can also be accessed in system memory space.
This register group is defined in the following subsections.
5.1
As a general rule, all PCI configuration registers default to
their power-on reset value when the card or docking station is
Register State on Device Removal
disconnected from the interface (CCD1# and CCD2# both
high). However, the 82C814-specific registers at PCICFG
48h-5Fh control global configuration and remain set to their
programmed values even after a device is removed.
5.2
The registers below represent the standard group required
for PCI peripheral device identification and configuration for a
PCI-to-CardBus bridge.
Base Register Group
Note:
In the tables that follow, all bits are R/W and their
default value is zero, unless otherwise specified.
R/W = Read/Write, RO = Read-only, and
WO = Write-only
Table 5-1
Base Register Group - PCICFG 00h-4Fh
7
6
5
4
3
2
1
0
PCICFG 00h
Vendor Identification Register (RO) - Byte 0
Default = 45h
PCICFG 01h
Vendor Identification Register (RO) Byte 1
Default = 10h
PCICFG 02h
Device ID (RO) - Byte 0
Default = 14h
PCICFG 03h
Device ID (RO) - Byte 1
Default = C8h
PCICFG 04h
PCI Command Register - Byte 0
Default = 04h
Address/data
stepping:
0 = Disable
(always)
PERR#
generation:
0 = Disable
1 = Enable
VGA palette
snoop:
0 = Disable
1 = Enable
Mem write and
Invalidate (RO):
0 = Disable
(always)
Special Cycle
(RO):
0 = Disable
(always)
Bus master by
docking inter-
faces:
1 = Enable
(always)
Respond to
PCI mem
accesses:
0 = No
1 = Yes
Respond to
PCI I/O
accesses:
0 = No
1 = Yes
PCICFG 05h
PCI Command Register - Byte 1
Default = 00h
Reserved: Write bits as read.
Fast back-to-
back (RO):
0 = Disable
(always)
SERR#
generation:
0 = Disable
1 = Enable
PCICFG 06h
PCI Status Register - Byte 0
Default = 10h
Fast back-to-
back capability
(RO):
0 = No (always)
Reserved (RO)
PCI Power
Management
Capability (RO)
1 = Yes
(always)
Reserved (RO)
PCICFG 07h
PCI Status Register - Byte 1
Default = 02h
Parity
error:
0 = No
1 = Yes
Write 1 to clear
System
error:
0 = No
1 = Yes
Write 1 to clear
Received
master abort:
0 = No
1 = Yes
Write 1 to clear
Received
target abort:
0 = No
1 = Yes
Write 1 to clear
Signalled
target abort:
0 = No
1 = Yes
Write 1 to clear
DEVSEL# timing (RO):
00 = Fast
01 = Medium (always)
10 = Slow
11 = Reserved
PERR# active
as master:
0 = No
1 = Yes
Write 1 to clear
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