- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361324 > QT0081411TUE Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號： | QT0081411TUE |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 26/62頁 |
| 文件大?。?/td> | 268K |
| 代理商： | QT0081411TUE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
82C814
Page 16
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
4.6.2
For a cycle from the host to a docking interface with a dock-
ing station attached, the PCI bridge resynchronizes the cycle
and passes it to the external PCI device. Docking PCI
devices can run either synchronously at the host PCI fre-
quency, or asynchronously at any speed using an external
clock. The bridge claims the cycle if it falls into one of the
ranges programmed in the Window Registers of the PCI Con-
figuration Register set.
Cycle from Host to Docking Interface
4.6.3
For a master cycle from the docking interface, the 82C814
logic presents the cycle on the host PCI bus as master.
Master Cycle from Docking Interface
If the cycle is directed to a device on the other docking inter-
face, the 82C814 logic claims the cycle immediately, as a
slave, since the address ranges are already programmed into
the Base Address Registers for that docking station.
If the cycle is not claimed by the other docking station and no
host device claims it, the 82C814 generates a master abort.
4.6.4
The 82C814 logic provides write posting in both the down-
stream and upstream PCI directions. There is a special situa-
tion that arises when the target of posted write data is unable
to complete the transaction. Normally, a target retry or a dis-
connect will result in the 82C814 logic retrying the access
until it has completed the transfer of posted data.
Inability to Complete a Posted Write
However, after the programmed number of retries has been
attempted, the logic must report the error condition back to
the host. The 82C814 provides only one mechanism to return
the error: the SERR# pin. The host must then decide how to
handle the SERR# generation, either by generation of an
NMI or some other means.
The 82C814 PCI configuration register set provides a register
to program the number of retries before the logic gives up
and generates SERR#, as shown in Table 4-4.
4.6.5
The PCI-to-CardBus bridge logic responds to cycle termina-
tion by target devices in various ways for each transaction
type being terminated.
Cycle Termination by Target
4.6.5.1
Retry or Disconnect - The 82C814 logic retries the write cycle
at least 256 times, and may continue trying indefinitely,
according to the setting of PCICFG 5Eh[2:0]. When the logic
reaches the retry limit, it generates SERR# on the master
interface. No target abort will be signalled in the PCI Status
Register, but software can read 82C814-Specific Register
5Fh to determine whether the retry limit was exceeded.
Posted Write Termination
Target Abort or No Response - The logic generates
SERR#+CSERR# on the master interface. Software reads
the PCI Status Register to determine that a target abort
occurred.
4.6.5.2
Retry, Disconnect, or Target Abort - The logic simply conveys
the target response to the initiator.
Non-Posted Write Termination
No Response - If PCICFG 3Eh[5] = 0, the 82C814 logic termi-
nates the cycle to the initiator normally. If bit 3Eh[5] = 1, the
logic generates target abort to the initiator.
4.6.5.3
Read (Prefetched or Non-Prefetched)
Termination
Retry, Disconnect, or Target Abort - The logic simply conveys
the target response to the initiator.
No Response - If PCICFG 3Eh[5] = 0, the 82C814 logic termi-
nates the cycle to the initiator normally and returns
FFFFFFFFh as the data read. If bit 3Eh[5] = 1, the logic gen-
erates target abort to the initiator.
Table 4-4
Write Posting Associated Registers
7
6
5
4
3
2
1
0
PCICFG 5Eh
Primary Retry Limit Register
Default = 07h
Retry Limit:
These bits relate to the number of times that the
82C814, as a slave, will retry accesses on the pri-
mary. If this limit is exceeded, the 82C814 gener-
ates SERR# to the host.
000=2
8
100=2
16
001=2
10
101=2
20
010=2
12
110=2
24
011=2
14
111= Infinite retries (Default)
相關PDF資料 |
PDF描述 |
|---|---|
| QT0086202TME | Controller Miscellaneous - Datasheet Reference |
| QT0086302TME | Controller Miscellaneous - Datasheet Reference |
| QT110-D | IC-QPROX SENSOR |
| QT110-S | IC-SMD-QPROX SENSOR |
| QT110 | SENSOR ICs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| QT0100 | 制造商:TE Connectivity 功能描述:Industrial Panel Mount Switches and Lights |
| QT0102 | 制造商:TE Connectivity 功能描述: |
| QT0105 | 制造商:TE Connectivity 功能描述:Industrial Panel Mount Switches and Lights |
| QT012 | 制造商:TE Connectivity 功能描述: |
| QT01201 | 功能描述:LIGHT PILOT RELIANT'22RECT BLCK RoHS:是 類別:光電元件 >> 面板指示器，指示燈 系列:Reliant'22 標準包裝:50 系列:- 透鏡顏色:綠 面板切口尺寸:6.4mm（圓形） 電壓:24V 形狀:圓形 類型:LED |
發(fā)布緊急采購，3分鐘左右您將得到回復。