參數(shù)資料
型號(hào)： QT0081411TUE
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 37/62頁(yè)
文件大小： 268K
代理商： QT0081411TUE
82C814
912-3000-047
Revision: 1.0
Page 27
January 08, 1998
OPTi
PCICFG 30h
I/O Window 0 Limit Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 0 Limit Address Bits:
-
The 32-bit I/O Window 0 Limit Address Register selects the end address of I/O Window 0.
-
The minimum window size is always 4 bytes.
RO:
Always returns 0.
PCICFG 31h
I/O Window 0 Limit Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 32h
I/O Window 0 Limit Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 33h
I/O Window 0 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 34h
I/O Window 1 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 1 Base Address Bits:
-
The 32-bit I/O Window 1 Base Address Register selects the start address of one of two possible
CardBus I/O windows to the slot interface.
-
The I/O windows are globally enabled by bit 04h[0] (Command Register).
RO:
Always returns
0.
Decoding:
0 = 16-bit
(AD[31:16] = 0)
1 = 32-bit
PCICFG 35h
I/O Window 1 Base Address Register - Byte 1: Address Bits [15:8]
Default = F0h
PCICFG 36h
I/O Window 1 Base Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG 37h
I/O Window 1 Base Address Register - Byte 3: Address Bits [31:24]
Default = FFh
PCICFG 38h
I/O Window 1 Limit Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 1 Limit Address Bits:
-
The 32-bit I/O Window 1 Limit Address Register selects the end address of I/O Window 1.
-
The minimum window size is always 4 bytes.
RO:
Always returns 0.
PCICFG 39h
I/O Window 1 Limit Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 3Ah
I/O Window 1 Limit Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 3Bh
I/O Window 1 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 3Ch
-
This register is readable and writable per the PCI specification.
-
The logic does not use the value written to this register.
Interrupt Line Register for Status Change
Default = 00h
PCICFG 3Dh
RO:
-
This register reflects the value written to PCICFG 4Ch.
-
It defaults to 01h, selecting PCIRQ0# for the status change (docking station attach/detach) interrupt.
-
If PCICFG 4Ch is written to select an ISA interrupt or no interrupt, this register returns 00h.
Interrupt Pin Register for Status Change
Default = 01h
PCICFG 3Eh
Bridge Control Register - Byte 0
Default = 40h
Reserved
Force CRST#
cycling
on slot
interface:
0 = CRST# high
1 = Assert
CRST#
(Default)
Response to
master abort
on slot
interface:
0 = Ignore
1 = Signal with
target abort
or SERR#
Reserved:
Write as read.
Pass VGA
addresses
A0000-BFFFFh,
3B0-3BBh,
3C0-3DFh:
0 = No
1 = Yes
Reserved
Forwarding of
SERR# from
slot interface to
primary PCI
bus:
0 = Disable
1 = Enable
Response to
parity errors on
slot interface:
0 = Ignore
1 = Enable
Table 5-1
Base Register Group - PCICFG 00h-4Fh (cont.)
7
6
5
4
3
2
1
0
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