參數(shù)資料
型號(hào)： QT0081411TUE
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 17/62頁(yè)
文件大?。?/td> 268K
代理商： QT0081411TUE
82C814
912-3000-047
Revision: 1.0
Page 7
January 08, 1998
OPTi
STOP#
128
I/O
Stop:
Used by the target to request that the master stop the current transaction
and retry it later. The 82C814 logic uses this mechanism to back-off from a
claimed cycle and generate, for example, an SMI through the IRQ driveback
cycle.
LOCK#
129
I/O
Lock:
Indicates an atomic operation that may require multiple transactions to
complete. The signal can be asserted to the 82C814 by any host bus PCI master,
and is driven by the 82C814 logic in response to the current slot interface bus
master driving its CBLOCK# signal.
DEVSEL#
127
I/O
Device Select:
Driven by the 82C814 logic when it decodes its address as the
target of the current access via either positive or subtractive decoding.
PERR#
130
I/O
Parity Error:
All devices use this signal to report data parity errors during any PCI
transaction except a Special Cycle.
SERR#
131
O/OD
System Error:
The 82C814 logic uses this line to report address parity errors,
data parity errors on the Special Cycle command, or any other system error
where the result will be catastrophic. This pin has an open drain output.
REQ#
98
O
Bus Request:
The 82C814 logic uses this signal to gain control of the PCI bus.
The logic also uses this pin to generate an interrupt driveback request.
GNT#
97
I
Bus Grant:
The system grants the bus to the 82C814 chip using this signal.
IDSEL
110
I
ID Select:
This signal is the "chip select" for the controller. This input simply con-
nects to one of the upper address lines to select the controller for configuration
cycles.
PCIRST#
95
I
Reset:
Main chip reset input.
3.2.2
Docking Control and Sense Signals
Signal Name
Pin
No.
Signal
Type
Signal Description
CCD1#
17
I
Connection Detect 1 and 2, Voltage Sense 1 and 2:
CCD1-2# and CVS1-2
are used to determine proper dock attachment and to sense its voltage.
CCD2#
94
I
CVS1
18
I
CVS2
93
I
ENVCC5
16
O
5.0V VCC Enable:
Used to turn on power to 5.0V dock.
ENVCC3
15
O
3.3V VCC Enable:
Used to turn on power to 3.3V dock.
INTD#
I/O
See Section 3.2.4 for interrupt information.
3.2.3
PCI Docking Interface Pins
Signal Name
Pin
No.
Signal
Type
Signal Description
CAD[31:0]
76, 72:66,
63:57, 42,
40:36,
32:30,
28:21
I/O
Multiplexed Address and Data Lines 31 through 0:
These pins are the multi-
plexed PCI address and data lines. During the address phase, these pins are
outputs for PCI slave cycles and inputs for PCI master cycles. During the data
phase, these pins are outputs during PCI write cycles and inputs during PCI
reads.
3.2.1
Host Interface PCI Signals (cont.)
Signal Name
Pin
No.
Signal
Type
Signal Description
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