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| 型號： | QT0081411TUE |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 47/62頁 |
| 文件大?。?/td> | 268K |
| 代理商： | QT0081411TUE |
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82C814
912-3000-047
Revision: 1.0
Page 37
January 08, 1998
OPTi
5.5.1.1
Each window can select either memory or I/O decoding, and
allows for a decode range anywhere from one dword to the
entire address space. Upper address bits from A31 on down
can be masked in the comparison, allowing any desired
degree of aliasing.
Cycle Decoding
5.5.1.2
Instead of passing a claimed cycle onto the intended slave
PCI interface, the cycle controller can generate a STOP# or
CSTOP# on the master PCI interface (primary PCI interface
or slot interface) and cause the controlling device to back off.
At the same time, the cycle controller generates an IRQ
driveback cycle with SMI# active, therefore converting the
cycle into a System Management Interrupt trap.
Cycle Trapping
At this point, the master will most likely retry the cycle, at
which time the 82C814 will allow it to proceed. It may or may
not be able to deliver valid data. The host chipset can then
run its SMM code. The SMM code can read the SMI Status
Register from the 82C814 to determine the window access
that caused the SMI. Once the value has been read, the host
must write a 1 back to each SMI indicator bit to re-enable
trapping and SMI generation on that window.
5.5.1.3
All docking station windows contain the ISA Window Selec-
tion bit. When set to 1, the window operation is modified as
follows.
ISA Window Selection
When a cycle initiated on the primary is claimed through
this window, the cycle will be immediately and automati-
cally retried.
On the docking station side, the OPTi PCI-ISA Bridge will
claim the cycle and wait for positive decode on the ISA
bus.
- If positive decode is determined, the OPTi PCI-ISA
Bridge logic will terminate the cycle normally.
- If no positive decode can be achieved, the OPTi PCI-
ISA Bridge logic will terminate the cycle with a Target
Abort. Once this occurs, the 82C814 chip will simply
ignore the next retry attempt on its primary and allow
the cycle to pass to the local ISA bus of the host control-
ler.
The retries occur up to the limit defined in PCICFG 5Eh[2:0]
before SERR# is generated.
Table 5-5
Docking Station Access Windows
Docking Station
Access Window #
Default Mask
Bits Decoded
Memory or I/O Selectable
Can Generate SMI#
0
000FFFh
A[31:2]
Yes - Defaults to Memory
Yes
1
000FFFh
A[31:2]
Yes - Defaults to Memory
Yes
2
000003h
A[31:2]
Yes - Defaults to I/O
Yes
3
000003h
A[31:2]
Yes - Defaults to I/O
Yes
Table 5-6
Docking Station Window Registers - PCICFG 80h-EFh
7
6
5
4
3
2
1
0
PCICFG 80h
Window 0 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window Start Address Bits:
-
Register bits [31:0] indicate the start address for Window 0.
-
The selection between memory or I/O, as well as other feature selections, are made through the
Window 0 Control Register.
RO:
Always
returns 0
If memory:
reads 0.
If I/O: Decoding
0 = 16-bit
AD[31:16] = 0
1 = 32-bit
PCICFG 81h
Window 0 Start Address Register - Byte 1: Address Bits [15:8]
Default = FFh
PCICFG 82h
Window 0 Start Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG 83h
Window 0 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
PCICFG 84h
Window 0 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 0 Address Bits:
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
RO:
Always returns 0
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