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參數(shù)資料
| 型號(hào)： | PPC440EP |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 440EP Embedded Processor |
| 中文描述： | 440EP的Power PC嵌入式處理器 |
| 文件頁(yè)數(shù)： | 77/84頁(yè) |
| 文件大?。?/td> | 541K |
| 代理商： | PPC440EP |
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AMCC Proprietary
77
440EP – PPC440EP Embedded Processor
Data Sheet
Revision 1.26 – April 25, 2007
Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at
(1)
. Except for small, low frequency memory systems with the memory located physically
close to the PPC440EP, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary
to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, T
T
is
system dependent and taken into account by controller initialization software.
Figure 11. DDR SDRAM Read Cycle Timing—Example 1
DQS at pin
PLB Clock
T
SIN
T
DIN
= Delay from data at package pin to D on Stage 1 FF.
T
T
= Propagation delay, Stage 1 input to RDSP input w/o ECC
T
SIN
= Delay from DQS at package pin to C on Stage 1 FF.
T
P
= Propagation delay through FFs
Data at pin
D0
D1
D2
D3
DQS Stage 1 C
D0
D1
D2
D3
T
DIN
D0
D2
Data in Stage 1 D
D1
D3
Data out Stage 1
High
Low
T
P
D0
D2
D1
D3
Data in at RDSP
with no ECC
High
Low
T
T
D0
D2
D1
D3
Data out RDSP
High
Low
(1)
D2
D2
T
P
D0
D0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EP-3BB533C | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3BC400C | 制造商:AMCC 功能描述:MPU 440EP RISC 16BIT 0.13UM 400MHZ 3.3V 456PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC440EP-3BC400C APD BIAS CTRL/MONITR |
| PPC440EP-3BC533C | 制造商:AppliedMicro 功能描述:MPU 440EP RISC 16-Bit 0.13um 533MHz 3.3V 456-Pin EBGA Tray |
| PPC440EP-3JA333CZ | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3JA400C | 制造商:AppliedMicro 功能描述: |
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