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參數(shù)資料
| 型號： | PPC440EP |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 440EP Embedded Processor |
| 中文描述： | 440EP的Power PC嵌入式處理器 |
| 文件頁數(shù)： | 56/84頁 |
| 文件大?。?/td> | 541K |
| 代理商： | PPC440EP |
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56
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
NAND Flash Interface
NFALE
Address Latch Enable.
O
Multiplex
NFCE0:3
Chip Enable (
multiplexed with the
PerCS0:3
signals)
.
O
Multiplex
NFCLE
Command Latch Enable.
O
Multiplex
NFRdyBusy
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-or connected from all NAND Flash devices.
I
Multiplex
NFREn
Read Enable strobe.
O
Multiplex
NFWEn
Write Enable strobe.
O
Multiplex
Serial Peripheral Interface
SCPClkOut
Clock output.
SCPClkOut, the serial port master clock out, is used to
synchronize all data movement both into and out of the device
through the serial data ports. Normally, data is shifted out on
the rising edge of the clock and shifted in on the negative
edge.
SCPClkOut is also used to shift data into and out of the slave
device. When the SPMODE register is reset, SCPClkOut is
forced to 0.
O
3.3V LVTTL
SCPDI
Data In.
Data is received from the connected slave device and is
captured synchronously with SysClk.
I
3.3V LVTTL
SCPDO
Data output.
Data is sent to the connected slave device synchronously with
SysClk.
O
3.3V LVTTL
Interrupts Interface
IRQ0:4
External interrupt requests 0 through 4.
I/O
3.3V LVTTL
1, 5
IRQ5
External interrupt request 5.
I
3.3V tolerant
2.5V CMOS
1
IRQ6:9
External interrupt requests 6 through 9.
I/O
3.3V LVTTL
1
JTAG Interface
TCK
Test Clock.
I
3.3V LVTTL
w/pull-up
1
TDI
Test Data In.
I
3.3V LVTTL
w/pull-up
4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V LVTTL
w/pull-up
1
TRST
Test Reset.
I
3.3V LVTTL
w/pull-up
5
Table 6. Signal Functional Description (Sheet 7 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
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|---|---|
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
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| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400E | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EP-3BB533C | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3BC400C | 制造商:AMCC 功能描述:MPU 440EP RISC 16BIT 0.13UM 400MHZ 3.3V 456PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC440EP-3BC400C APD BIAS CTRL/MONITR |
| PPC440EP-3BC533C | 制造商:AppliedMicro 功能描述:MPU 440EP RISC 16-Bit 0.13um 533MHz 3.3V 456-Pin EBGA Tray |
| PPC440EP-3JA333CZ | 制造商:AppliedMicro 功能描述: |
| PPC440EP-3JA400C | 制造商:AppliedMicro 功能描述: |
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