參數(shù)資料
型號: PPC440EP
廠商: Applied Micro Circuits Corp.
英文描述: Power PC 440EP Embedded Processor
中文描述: 440EP的Power PC嵌入式處理器
文件頁數(shù): 73/84頁
文件大小: 541K
代理商: PPC440EP
AMCC Proprietary
73
440EP – PPC440EP Embedded Processor
Data Sheet
Revision 1.26 – April 25, 2007
DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 8. DDR SDRAM Write Cycle Timing
DQS
MemData
PLB Clk
MemClkOut0
MemClkOut0(90)
Addr/Cmd
T
SK
T
SA
T
HA
T
DS
T
DS
T
SD
T
HD
T
SD
T
HD
T
SA
= Setup time for address and command signals to MemClkOut0(90)
T
HA
= Hold time for address and command signals from MemClkOut0(90)
T
SD
= Setup time for data signals (minimum time data is valid
before
rising/falling edge of DSQ)
T
HD
= Hold time for data signals (minimum time data is valid
after
rising/falling edge of DSQ)
T
SK
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
T
DS
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
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