參數(shù)資料
型號(hào)： PPC440EP
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440EP Embedded Processor
中文描述： 440EP的Power PC嵌入式處理器
文件頁(yè)數(shù)： 64/84頁(yè)
文件大?。?/td> 541K
代理商： PPC440EP
64
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440EP. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC440EP the following conditions must be met:
The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC440EP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
The maximum frequency deviation cannot exceed
3%, and the modulation frequency cannot exceed 40kHz.
In some cases, on-board PPC440EP peripherals impose more stringent requirements.
Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
modulation.
Use the DDR SDRAM MemClkOut since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Important:
It is up to the system designer to ensure that any SSCG used with the PPC440EP meets the above
requirements and does not adversely affect other aspects of the system.
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