參數(shù)資料
型號(hào)： PPC440EP
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440EP Embedded Processor
中文描述： 440EP的Power PC嵌入式處理器
文件頁(yè)數(shù)： 10/84頁(yè)
文件大?。?/td> 541K
代理商： PPC440EP
10
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
Internal Buses
The PowerPC 440EP features five standard on-chip buses: two Processor Local Buses (PLBs), two On-Chip
Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth
cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect
to the PLBs. The primary OPB hosts lower data rate peripherals. The secondary OPB is dedicated to USB 2.0 and
DMA. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between
the processor core and the other on-chip cores.
Features include:
PLB 128 (PLB4)
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 133MHz, maximum 4.25GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1 and N:2
PLB 64 (PLB3)
– 64-bit implementation of the PLB architecture
– 32-bit address
– 133MHz (1:1 ratio with PLB 128), maximum 1.1GB/s (no simultaneous read and write)
OPB (2)
– 32-bit data path
– 32-bit address
– 66.66MHz
DCR
– 32-bit data path
– 10-bit address
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