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參數(shù)資料
| 型號： | PowerPC 750 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 8/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | POWERPC 750 |
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Page 4
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
- Special register transfer instructions.
Cache structure
- 32K, 32-byte line, 8-way set associative instruction cache.
- 32K, 32-byte line, 8-way set associative data cache.
- Single-cycle cache access.
- Pseudo-LRU replacement.
- Copy-back or write-through data cache (on a page per page basis).
- Supports all PowerPC memory coherency modes.
- Non-blocking instruction and data cache (one outstanding miss under hits).
- No snooping of instruction cache.
Memory management unit
- 128 entry, 2-way set associative instruction TLB.
- 128 entry, 2-way set associative data TLB.
- Hardware reload for TLB's.
- 4 instruction BAT's and 4 data BATs.
- Virtual memory support for up to 4 exabytes (2
52
) virtual memory.
- Real memory support for up to 4 gigabytes (2
32
) of physical memory.
Level 2 (L2) cache interface
- Internal L2 cache controller and 4K-entry tags; external data SRAMs.
- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support.
- Copy-back or write-through data cache (on a page basis, or for all L2).
- 64-byte (256K/512K) and 128-byte (l-Mbyte) sectored line size.
- Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst
SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs.
- Design supports Core-to-L2 frequency divisors of
÷
1,
÷
1.5,
÷
2,
÷
2.5, and
÷
3. However, this specifica-
tion supports the L2 frequency range specified in Section “L2 Clock AC Specifications,” on page 15.
For higher L2 frequencies not supported in this document, please contact your IBM marketing repre-
sentative.
Bus interface
- Compatible with 60x processor interface.
- 32-bit address bus.
- 64-bit data bus.
- Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x and 10x sup-
ported (10x on rev level dd3.x only).
Integrated power management
- Low-power 2.0/3.3V design.
- Three static power saving modes: doze, nap, and sleep.
- Automatic dynamic power reduction when internal functional units are idle.
Integrated Thermal Management Assist Unit
- On-chip thermal sensor and control logic.
- Thermal Management Interrupt for software regulation of junction temperature.
Testability
- LSSD scan design.
- JTAG interface.
Reliability and serviceability–Parity checking on 60x and L2 cache buses
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