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參數(shù)資料
| 型號： | PowerPC 750 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 29/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | POWERPC 750 |
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9/30/99
Version 2.0
Datasheet
Page 25
PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
GND
D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11,
H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16,
L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16,
R8, R12, T4, T6, T10, T14, T16
—
—
HRESET
B6
Low
Input
INT
C11
Low
Input
L1_TSTCLK
1
F8
High
Input
L2ADDR[0-16]
L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17,
J14, J13, H19, G18
High
Output
L2AVDD
L13
—
—
L2CE
P17
Low
Output
L2CLKOUTA
N15
—
Output
L2CLKOUTB
L16
—
Output
L2DATA[0-63]
U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18,
V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13,
N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14,
G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17,
B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14,
E13
High
I/O
L2DP[0-7]
V14, U16, T19, N18, H14, F17, C19, B15
High
I/O
L2OVDD
D15, E14, E16, H16, J15, L15, M16, P15, R14, R16, T15, F15
—
—
L2SYNC_IN
L14
—
Input
L2SYNC_OUT
M14
—
Output
L2_TSTCLK
1
F7
High
Input
L2WE
N16
Low
Output
L2ZZ
G17
High
Output
LSSD_MODE
1
F9
Low
Input
MCP
B11
Low
Input
NC (No-Connect)
B3, B4, B5, W19, K9, K11
4
, K19
4
—
—
OVDD
2
D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9,
R11, T5, T8, T12
—
—
Pinout Listing for the 360 CBGA package
5
Signal Name
Pin Number
Active
I/O
Note:
1. These are test signals for factory use only and must be pulled up to OV
DD
for normal machine operation.
2. OV
DD
inputs supply power to the I/O drivers and V
DD
inputs supply power to the processor core.
3. Internally tied to L2OV
DD
in the PID8p-750 360 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
5. Pull up and pull down resistor requirements for all pins are listed in the “Pull-up / Pull-down Resistor Requirements” section on page 33
6. BVSEL selects the I/O voltage on the 60X bus. L2VSEL selects the I/O voltage on the L2 bus. Please refer to the Table “Recommended Operating
Conditions1,2,3,” on page 6, for the use of these pins.
7. TCK must be tied high or low for normal machine operation.
8. Address and data parity signals must be tied high or low if unused in the design.
9. Starting with rev levels dd3.X, the AV
DD
pin is no longer brought out to the package.
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