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參數資料
| 型號： | PowerPC 750 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數： | 24/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | POWERPC 750 |
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Page 20
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
IEEE 1149.1 AC Timing Specifications
The table below provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 9, Figure 10,
Figure 11, and Figure 12. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
Figure 9 provides the JTAG clock input timing diagram.
JTAG AC Timing Specifications (Independent of SYSCLK)
See Table “Recommended Operating Conditions1,2,3,” on page 6 for operating conditions, C
L
= 50pF.
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
—
ns
2
TCK clock pulse width measured at 1.4V
15
—
ns
3
TCK rise and fall times
0
2
ns
4
4
spec obsolete, intentionally omitted
5
TRST assert time
25
—
ns
1
6
Boundary-scan input data setup time
4
—
ns
2
7
Boundary-scan input data hold time
16
—
ns
2
8
TCK to output data valid
4
20
ns
3, 5
9
TCK to output high impedance
3
19
ns
3, 4
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
16
—
ns
12
TCK to TDO data valid
2.5
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 9. JTAG Clock Input Timing Diagram
1
2
2
3
3
VM
TCK
VM
VM
Midpoint voltage (VM) is 1.4v for (2OVdd)
in 3.3v and (2OVdd/2) for all other I/O modes.
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