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參數(shù)資料
| 型號： | PowerPC 750 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 34/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | POWERPC 750 |
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Page 30
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
System Design Information
This section provides electrical and thermal design recommendations for successful application of the PID8p-
750.
PLL Configuration
The PID8p-750 PLL is configured by the PLL_CFG[0-3-] signals. For a given SYSCLK (bus) frequency, the
PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for
the PID8p-750 is shown in the following table for nominal frequencies.
PID8p-750 Microprocessor PLL Configuration
PLL_CFG
(0:3)
Processor to Bus
Frequency Ratio
(r)
VCO Divider
(d)
Frequency Range Supported by VCO having an example range of
VCOmin
7
= 400 to VCOmax =1000 MHz
6
SYSCLK
Core
bin
dec
Min = VCO
min
/(r*d) Max = VCO
max
/(r*d)
Min = VCO
min
/d
Max = VCO
max
/d
0000
0
Rsv
1
n/a
n/a
n/a
n/a
n/a
0001
1
7.5x
2
27
66
200
500
0010
2
7x
2
29
71
0011
3
PLL Bypass
3
n/a
n/a
n/a
n/a
n/a
0100
4
Rsv
1
n/a
n/a
n/a
n/a
n/a
0101
5
6.5x
2
31
77
200
500
0110
6
10x
8
2
25
2
50
200
500
0111
7
4.5x
2
44
100
5
200
500
1000
8
3x
2
66
100
5
1001
9
5.5x
2
36
91
1010
10
4x
2
50
100
5
1011
11
5x
2
40
100
1100
12
8x
2
25
2
63
1101
13
6x
2
33
83
1110
14
3.5x
2
57
100
5
1111
15
Off
4
n/a
n/a
n/a
Off
Off
Note:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section , “Clock AC Specifications,” for valid SYSCLK and VCO
frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode
operation. This mode is intended for factory use only.
Note:
The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. In Clock - off mode, no clocking occurs inside the PID8p-750 regardless of the SYSCLK input.
5. The SYSCLK limit is 100MHz as specified in Section “Clock AC Specifications,” on page 10.
6. VCO
is specified in this table by the maximum core processor speed. See “Clock AC Specifications” on page 10. This is not the VCO limit of the
technology.
7. VCO
MIN
is specified in this table by the minimum core processor speed. See “Clock AC Specifications” on page 10.
8. Available on rev level DD3.x or higher
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