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參數(shù)資料
| 型號(hào)： | PM73121 |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | AAL1 Segmentation And Reassembly Processor |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE |
| 文件頁(yè)數(shù)： | 25/223頁(yè) |
| 文件大?。?/td> | 2300K |
| 代理商： | PM73121 |
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PM73121AAL1gator II
PMC-Sierra, Inc.
L
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
35235,(7$5<$1'&21),'(17,$/7230&6,(55$,1&$1')25,76&86720(56,17(51$/86(
The R_SEQUENCE_ERR counter (refer to
“R_SEQUENCE_ERR Word Format” on
page 157
) has been changed to conform to the CES MIB. That is, only transitions from
SYNC to OUT_OF_SEQUENCE are counted, as specified in ITU-T Recommendation
I.363.1.
The revision code of the chip has been changed to “121A”.
When using the AAL1gator II, you will have to make software updates to take advantage of
the new features (refer to
“New Features” starting on page 4
). These new features require set-
ting control bits or writing fields that are not used in the WAC-021-CX. The default for these
bits is off.
PM73121 Required Board Modifications
The PM73121 is pin-for-pin backward compatible with the WAC-021-CX. To allow the
AAL1gator II to drop into a board developed for the WAC-021-CX, the following hooks
need to be implemented for you to take advantage of internal clock synthesis or UTOPIA
PHY mode.
To Use Internal Clock Synthesis
Provide a means to tristate TL_CLK to the PM73121.
Provide pads to terminate TL_CLK correctly when sourced by the PM73121. You may
need to remove the termination used when the AAL1gator II does not source TL_CLK.
Be aware of any skew issues that may arise when the AAL1gator II sources the TL_CLK
instead of being externally generated, such as an external clock multiplexer.
NOTE: With respect to TL_CLK, the AAL1gator II timing remains the same whether it
sources the clock or not.
Pin 79 is the TLCLK_OUTPUT_EN pin. The AAL1gator II can synthesize a nominal
clock, loop the RL_CLK, or use the SRTS to generate the TL_CLK. To select the clock
type, configure the LIN_STR_MODE register (refer to
“LIN_STR_MODE” starting on
page 126
). Since there is a period of time between reset and when this register is read,
there may not be a TL_CLK. To account for this, tie the TLCLK_OUTPUT_EN high.
This will cause the RL_CLK to be looped to the TL_CLK pins until the value has been
read. Then each line TL_CLK will switch to the proper value. (Each line can be different).
If you do not want a clock to drive between reset and when this register is read, tie
TLCLK_OUTPUT_EN low. In summary, provide a means to pull up or pull down pin 79.
It will default to pull down via an internal pull-down resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM73121-RI | AAL1 Segmentation And Reassembly Processor |
| PM73122 | 32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| PM73122-BI | 32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| PM73123 | 8 LINK CES/DBCES AAL1 SAR |
| PM73123-PI | 8 LINK CES/DBCES AAL1 SAR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM73121-RI | 制造商:PMC 制造商全稱:PMC 功能描述:AAL1 Segmentation And Reassembly Processor |
| PM73122 | 制造商:PMC 制造商全稱:PMC 功能描述:32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| PM73122-BI | 制造商:PMC 制造商全稱:PMC 功能描述:32 LINK CES/DBCES AAL1 SAR PROCESSOR |
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