參數(shù)資料
型號(hào)： PI7C7300A
廠商： Pericom Semiconductor Corp.
英文描述： 3-PORT PCI-to-PCI BRIDGE
中文描述： 3端口PCI至PCI橋
文件頁(yè)數(shù)： 97/109頁(yè)
文件大小： 779K
代理商： PI7C7300A
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 97 OF 109
09/25/03 Revision 1.09
16.3
TAP TEST DATA REGISTERS
The PI7C7300A contains two test data registers (bypass and boundary-scan). Each test
data register selected by the TAP controller is connected serially between TDI and TDO.
TDI is connected to the test data register’s most significant bit. TDO is connected to the
least significant bit. Data is shifted one bit position within the register towards TDO on
each rising edge of TCK. While any register is selected, data is transferred from TDI to
TDO without inversion. The following sections describe each of the test data registers.
16.4
BYPASS REGISTER
The required bypass register, a one-bit shift register, provides the shortest path between
TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test
data to and from other components on the board. This path can be selected when no test
operation is being performed on the PI7C7300A.
16.5
BOUNDARY-SCAN REGISTER
The boundary-scan register contains a cell for each pin as well as control cells for I/O
and the high-impedance pin.
Table 16-2 shows the bit order of the PI7C7300A boundary-scan register. All table cells
that contain “Control” select the direction of bi-directional pins or high-impedance
output pins. When a “0” is loaded into the control cell, the associated pin(s) are high-
impedance or selected as input.
The boundary-scan register is a required set of serial-shiftable register cells, configured
in master/slave stages and connected between each of the PI7C7300A’s pins and on-chip
system logic. The VDD, GND, PLL, AGND, AVDD and JTAG pins are NOT in the
boundary-scan chain.
The boundary-scan register cells are dedicated logic and do not have any system
function. Data may be loaded into the boundary-scan register master cells from the
device input pins and output pin-drivers in parallel by the mandatory sample/preload and
extest instructions. Parallel loading takes place on the rising edge of TCK.
Data may be scanned into the boundary-scan register serially via the TDI serial input pin,
clocked by the rising edge of TCK. When the required data has been loaded into the
master-cell stages, it can be driven into the system logic at input pins or onto the output
pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan
register by means of the TDO serial output pin at the falling edge of TCK.
16.6
TAP CONTROLLER
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that
controls the sequence of test logic operations. The TAP can be controlled via a bus
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300AEVB-3 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C7300ANA 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300ANAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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