參數(shù)資料
型號(hào): PI7C7300A
廠商: Pericom Semiconductor Corp.
英文描述: 3-PORT PCI-to-PCI BRIDGE
中文描述: 3端口PCI至PCI橋
文件頁(yè)數(shù): 40/109頁(yè)
文件大?。?/td> 779K
代理商: PI7C7300A
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 40 OF 109
09/25/03 Revision 1.09
PI7C7300A returns a target disconnect to an initiator when one of the following
conditions is met:
!
PI7C7300A hits an internal address boundary.
!
PI7C7300A cannot accept any more write data.
!
PI7C7300A has no more read data to deliver.
See Section 4.6.4 for a description of write address boundaries, and Section 4.7.3 for a
description of read address boundaries.
TARGET ABORT
4.9.4.3
PI7C7300A returns a target abort to an initiator when one of the following conditions is
met:
!
PI7C7300A is returning a target abort from the intended target.
When PI7C7300A returns a target abort to the initiator, it sets the signaled target abort
bit in the status register corresponding to the initiator interface.
4.10
CONCURRENT MODE OPERATION
The Bridge can be configured to run in concurrent operation. Concurrent operation is
defined as cycles going from one device on one secondary bus to another device on the
same or other secondary bus. This off-loads traffic from the primary bus, allowing other
traffic to run on the primary bus concurrently.
The Bridge is already configured to handle concurrent operation. However, the devices
themselves need to be configured to do so. Meaning, device drivers for the specific
device used will have to be configured to perform the operation. Please see section 5.1
for more information on addressing.
5
ADDRESS DECODING
PI7C7300A uses three address ranges that control I/O and memory transaction
forwarding. These address ranges are defined by base and limit address registers in the
configuration space. This chapter describes these address ranges, as well as ISA-mode
and VGA-addressing support.
5.1
ADDRESS RANGES
PI7C7300A uses the following address ranges that determine which I/O and memory
transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from
the secondary bus to the primary bus:
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