參數(shù)資料
型號: PI7C7300A
廠商: Pericom Semiconductor Corp.
英文描述: 3-PORT PCI-to-PCI BRIDGE
中文描述: 3端口PCI至PCI橋
文件頁數(shù): 81/109頁
文件大?。?/td> 779K
代理商: PI7C7300A
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 81 OF 109
09/25/03 Revision 1.09
Bit
19
Function
VGA enable
Type
R/W
Description
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses from
primary to secondary
1: forward VGA compatible memory and I/O addresses from primary
to secondary regardless of other settings
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Control’s bridge’s behavior responding to master aborts on secondary
interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible by the
assertion of P_SERR# if enabled
Reset to 0
Controls the assertion of S1_RESET# or S2_RESET# signal pin on
the secondary interface
0: does not force the assertion of S1_RESET# or S2_RESET# pin
1: forces the assertion of S1_RESET# or S2_RESET#
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not allow fast back-to-back transactions
1: enables fast back-to-back transactions
Reset to 0
Reserved. Reset to 0
Reserved. Reset to 0
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
This bit Is set to 1 and P_SERR# is asserted when either the primary
discard timer or the secondary S1 or S2 discard timer expire.
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
20
21
Reserved
Master Abort
Mode
R/O
R/W
22
Secondary
Interface Reset
R/W
23
Fast Back-to-
Back Enable
R/W
24
25
26
Reserved
Reserved
Master Timeout
Status
R/W
R/W
R/WC
27
Discard Timer
P_SERR# enable
R/WC
31-28
Reserved
R/O
14.1.27
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Configuration 1
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Memory Write
Disconnect
Control
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
3:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
R/W
Controls when the bridge (as a target) disconnects memory write
transactions.
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