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參數(shù)資料
| 型號： | PI7C7300A |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3-PORT PCI-to-PCI BRIDGE |
| 中文描述： | 3端口PCI至PCI橋 |
| 文件頁數(shù)： | 24/109頁 |
| 文件大?。?/td> | 779K |
| 代理商： | PI7C7300A |
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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 24 OF 109
09/25/03 Revision 1.09
address out on the target bus. On the following cycle, PI7C7300A drives the first
DWORD of write data and continues to transfer write data until all write data
corresponding to that transaction is delivered, or until a target termination is received. As
long as write data exists in the queue, PI7C7300A can drive one DWORD of write data
each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing
through PI7C7300A and the initiator stalls, PI7C7300A will signal the last data phase for
the current transaction at the target bus if the queue empties. PI7C7300A will restart the
follow-on transactions if the queue has new data.
PI7C7300A ends the transaction on the target bus when one of the following conditions
is met:
!
!
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C7300A starts another
transaction to deliver the rest of the write data).
!
!
The target returns a target abort (PI7C7300A discards remaining write data).
The master latency timer expires, and PI7C7300A no longer has the target bus grant
(PI7C7300A starts another transaction to deliver remaining write data).
Section 4.9.3.2 provides detailed information about how PI7C7300A responds to target
termination during posted write transactions.
4.6.2
MEMORY WRITE AND INVALIDATE TRANSACTIONS
Posted write forwarding is used for Memory Write and Invalidate transactions.
The PI7C7300A disconnects Memory Write and Invalidate commands at aligned cache
line boundaries. The cache line size value in the cache line size register gives the number
of DWORD in a cache line.
If the value in the cache line size register does meet the memory write and invalidate
conditions, the PI7C7300A returns a target disconnect to the initiator either on a cache
line boundary or when the posted write buffer fills.
When the Memory Write and Invalidate transaction is disconnected before a cache line
boundary is reached, typically because the posted write buffer fills, the trans-action is
converted to Memory Write transaction.
4.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration
write transactions.
A delayed write transaction guarantees that the actual target response is returned back to
the initiator without holding the initiating bus in wait states. A delayed write transaction
is limited to a single DWORD data transfer.
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PDF描述 |
|---|---|
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
| PI7C8140A | 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8148B | 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON |
| PI7C8150B-33 | PCI Bridge | Asynchronous 2-Port PCI Bridge |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300ANAE | 功能描述:外圍驅(qū)動器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300ANA-E | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300DNAE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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