參數(shù)資料
型號(hào)： PI7C7300A
廠商： Pericom Semiconductor Corp.
英文描述： 3-PORT PCI-to-PCI BRIDGE
中文描述： 3端口PCI至PCI橋
文件頁(yè)數(shù)： 93/109頁(yè)
文件大?。?/td> 779K
代理商： PI7C7300A
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 93 OF 109
09/25/03 Revision 1.09
15.2
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C7300A complies with the ordering
rules put forth in the
PCI Local Bus Specification, Rev 2.2
. The following table
summarizes the ordering relationship of all the transactions through the bridge.
PMW
- Posted write (either memory write or memory write & invalidate)
DRR
- Delayed read request (all memory read, I/O read & configuration read)
DWR
- Delayed write request (I/O write & configuration write, memory write to
certain location)
DRC
- Delayed read completion (all memory read, I/O read & configuration read)
DWC
- Delayed write completion (I/O write & configuration write, memory write
to ccertain location
Cycle type shown on each row is the subsequent cycle after the previous shown on the
column.
PMW
Column 1
Column 2
PMW (Row 1)
No
Yes
DRR (Row 2)
No
No
DWR (Row 3)
No
No
DRC (Row 4)
No
Yes
DWC (Row 5)
Yes
Yes
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must
complete on the target bus in the order in which they were received in the initiator bus.
In Row 2 Column1,DRR cannot pass the previous PMW and that means the previous
PMW heading to the same direction must be completed before the DRR can be attempted
on the target bus.
In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the
head of the delayed transaction queue.
Can Row Pass Column
DRR
DWR
Column 3
Yes
No
No
Yes
Yes
DRC
Column 4
Yes
Yes
Yes
No
No
DWC
Column 5
Yes
Yes
Yes
No
No
15.3
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
15.3.1
MASTER ABORT
Master abort indicates that when PI7C7300A acts as a master and receives no response
(i.e., no target asserts DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the
bridge deasserts FRAME# and then deasserts IRDY#.
15.3.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
S1_PAR, and S2_PAR signals. Parity should be even (i. e. an even number of‘1’s) across
AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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PI7C7300ANA 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300ANAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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PI7C7300DNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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