參數(shù)資料
型號(hào): PI7C7300A
廠商: Pericom Semiconductor Corp.
英文描述: 3-PORT PCI-to-PCI BRIDGE
中文描述: 3端口PCI至PCI橋
文件頁(yè)數(shù): 87/109頁(yè)
文件大?。?/td> 779K
代理商: PI7C7300A
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 87 OF 109
09/25/03 Revision 1.09
Bit
Function
Type
Description
Controls PI7C7300A’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
Controls PI7C7300A’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
Controls PI7C7300A’s detection mechanism for matching memory
read retry cycles from the initiator on S1
0: exact matching for memory read retry cycles from initiator on the
S1 or S2 interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the S1 or S2 interface
Reset to 0
Controls PI7C7300A’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the S1 or S2 interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the S1 or S2 interface
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C7300A’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Control’s PI7C7300A’s ability to enable S1 or S2 to hold requests
longer.
0: internal S1 or S2 master will release REQ_L after FRAME_L
assertion
1: internal S1 or S2 master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
1
Primary MEMR
Command Alias
Enable
R/W
2
Primary MEMW
Command Alias
Enable
R/W
3
Secondary
MEMR
Command Alias
Enable
R/W
4
Secondary
MEMW
Command Alias
Enable
R/W
8:5
Reserved
R/O
9
Enable Long
Request
R/W
10
Enable
Secondary To
Hold Request
Longer
R/W
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