參數(shù)資料
型號： Pentium OverDrive Processor
廠商： Intel Corp.
英文描述： Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器)
中文描述： 奔騰過驅(qū)動(dòng)處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)（帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器）
文件頁數(shù)： 42/61頁
文件大?。?/td> 481K
代理商： PENTIUM OVERDRIVE PROCESSOR
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
E
42
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
5.6.3.
A. C. TABLES FOR A 66-MHZ BUS
The A.C. specifications given in Table 17 consist of
output delays, input setup requirements and input
hold requirements for a 66-MHz external bus. All
A.C. specifications (with the exception of those for
the TAP signals) are relative to the rising edge of the
CLK input.
All timings are referenced to 1.5 volts for both “0” and
“1” logic levels unless otherwise specified. Within the
sampling window, a synchronous input must be
stable for correct 200-MHz Pentium OverDrive
processor with MMX technology operation.
Table 17. 66-MHz Bus A.C. Specifications
3.135 < V
CC
< 3.6V, T
A
= 10 to 45
°
C, C
L
= 0 pF
Symbol
Parameter
Min
Max
Unit
Figure
Notes
Frequency
33.33 66.6
MHz
Max core Freq = 166 MHz
@ 2/5
t
1a
CLK Period
15.0
30.0
nS
7
t
1b
CLK Period Stability
±
250
pS
7
Adjacent Clocks, (1), (25)
t
2
CLK High Time
4.0
nS
7
@2V, (1), (5)
t
3
CLK Low Time
4.0
nS
7
@0.8V, (1), (5)
t
4
CLK Fall Time
0.15
1.5
nS
7
(2.0V-0.8V),(1),(5)
t
5
CLK Rise Time
0.15
1.5
nS
7
(0.8V-.0V),(1),(5)
t
6a
ADSC#, PWT, PCD, BE0-7#, D/C#,
W/R#, CACHE#, SCYC, Valid Delay
1.0
7.0
nS
8
t
6b
AP Valid Delay
1.0
8.5
nS
8
t
6c
A3-A31, LOCK# Valid Delay
1.1
7.0
nS
8
t
6d
ADS#, MIO# Valid Delay
1.0
6.0
nS
8
t
7
ADS#, ADSC#, AP, A3-A31, PWT,
PCD, BE0-7#, M/IO#, D/C#, W/R#,
CACHE#, SCYC, LOCK# Float Delay
10.0
nS
9
(1)
t
8a
APCHK#, IERR#, FERR# Valid Delay
1.0
8.3
nS
8
(4)
t
8b
PCHK# Valid Delay
1.0
7.0
nS
8
(4)
t
9a
BREQ, HLDA Valid Delay
1.0
8.0
nS
8
(4), (21)
t
9b
SMIACT# Valid Delay
1.0
7.6
nS
8
(4), (21)
t
10a
HIT# Valid Delay
1.0
8.0
nS
8
(21)
t
10b
HITM# Valid Delay
1.1
6.0
nS
8
t
11a
PM0-1, BP0-3 Valid Delay
1.0
10.0
nS
8
t
11b
PRDY Valid Delay
1.0
8.0
nS
8
t
12
D0-D63, DP0-7 Write Data Valid Delay 1.3
7.5
nS
8
(21)
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