參數(shù)資料
型號(hào): Pentium OverDrive Processor
廠商: Intel Corp.
英文描述: Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器)
中文描述: 奔騰過(guò)驅(qū)動(dòng)處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)(帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器)
文件頁(yè)數(shù): 36/61頁(yè)
文件大?。?/td> 481K
代理商: PENTIUM OVERDRIVE PROCESSOR
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
E
36
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 15. 50-MHz Bus A.C. Specifications
3.135 < V
CC
< 3.6V, TA = 10 to 45
°
C, CL = 0 pF
Parameter
Symbol
Min
Max
Unit
Figure
Notes
t
33
R/S# Pulse Width, Async.
2.0
CLKs
(14), (16)
t
34
D0-D63, DP0-7 Read Data Setup Time
3.8
nS
10
t
35
D0-D63, DP0-7 Read Data Hold Time
2.0
nS
10
t
36
RESET Setup Time
5.0
nS
11
(11), (15)
t
37
RESET Hold Time
1.0
nS
11
(12)
t
38
RESET Pulse Width, V
CC
& CLK Stable
15.0
CLKs
11
(16)
t
39
RESET Active After V
CC
& CLK Stable
1.0
mS
11
Power up
t
40
Reset Configuration Signals (INIT,
FLUSH#) Setup Time
5.0
nS
11
(11), (15), (16)
t
41
Reset Configuration Signals (INIT,
FLUSH#) Hold Time
1.0
nS
11
(12)
t
42a
Reset Configuration Signals (INIT,
FLUSH#) Setup Time, Async.
2.0
CLKs
11
To RESET falling
edge (15)
t
42b
Reset Configuration Signals (INIT,
FLUSH#, BRDYC#, BUSCHK#) Hold
Time, Async.
2.0
CLKs
11
To RESET falling
edge (20)
t
42c
Reset Configuration Signals (BRDYC#,
BUSCHK#) Setup Time, Async.
3.0
CLKs
11
To RESET falling
edge (20)
t
42d
Reset Configuration Signals (BRDYC#)
Hold Time, RESET Driven
Synchronously.
1.0
nS
To RESET falling
edge (1), (27)
t
44
TCK Frequency
16.0
MHz
t
45
TCK Period
62.5
nS
7
t
46
TCK High Time
25.0
nS
7
@2V, (1)
t
47
TCK Low Time
25.0
nS
7
@0.8V, (1)
t
48
TCK Fall Time
5.0
nS
7
(2.0V-0.8V), (1),
(8), (9)
t
49
TCK Rise Time
5.0
nS
7
(0.8V-2.0V), (1),
(8), (9)
t
50
TRST# Pulse Width
40.0
nS
13
(1), Asynchronous
t
51
TDI, TMS Setup Time
5.0
nS
12
(7)
t
52
TDI, TMS Hold Time
13.0
nS
12
(7)
t
53
TDO Valid Delay
3.0
20.0
nS
12
(8)
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