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參數資料
| 型號： | Pentium OverDrive Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術奔騰超速轉動處理器) |
| 中文描述： | 奔騰過驅動處理器的MMX技術的Pentium處理器為基礎的系統(tǒng)（帶MMX公司技術奔騰超速轉動處理器） |
| 文件頁數： | 19/61頁 |
| 文件大?。?/td> | 481K |
| 代理商： | PENTIUM OVERDRIVE PROCESSOR |
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E
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
19
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 2. Quick Pin Reference
Symbol
Type
Name and Function
PCD
O
The page cache disable pin reflects the state of the PCD bit in CR3, the Page
Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an
external cacheability indication on a page by page basis.
PCHK#
O
The parity check output indicates the result of a parity check on a data read. It is
driven with parity status two clocks after BRDY# is returned. PCHK# remains
low one clock for each clock in which a parity error was detected. Parity is
checked only for the bytes on which valid data is returned.
PEN#
I
The parity enable input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle. If
this pin is sampled active in the clock a data parity error is detected, the
Pentium OverDrive processor with MMX technology will latch the address and
control signals of the cycle with the parity error in the machine check registers.
If, in addition, the machine check enable bit in CR4 is set to “1”, the Pentium
OverDrive processor with MMX technology will vector to the machine check
exception before the beginning of the next instruction.
PHIT#
I/O
The Pentium OverDrive processor with MMX technology does not support dual
processing.
PHITM#
I/O
The Pentium OverDrive processor with MMX technology does not support dual
processing.
PICCLK
I
The Pentium OverDrive processor with MMX technology does not support dual
processing.
PICD0-1
[DPEN#]
[APICEN]
I/O
The Pentium OverDrive processor with MMX technology does not support dual
processing.
PBREQ#
I/O
The Pentium OverDrive processor with MMX technology does not support dual
processing.
PM/BP[1:0]
O
These pins function as part of the performance monitoring feature.
The breakpoint 1-0 pins are multiplexed with the
performance monitoring 1-0
pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins
come out of RESET configured for performance monitoring.
PRDY
O
The probe ready output pin indicates that the processor has stopped normal
execution in response to the R/S# pin going active, or Probe Mode being
entered.
PWT
O
The page write through pin reflects the state of the PWT bit in CR3, the Page
Directory Entry, or the Page Table Entry. The PWT pin is used to provide an
external writeback indication on a page by page basis.
R/S#
I
The run / stop input is an asynchronous, edge sensitive interrupt used to stop
the normal execution of the processor and place it into an idle state. A high to
low transition on the R/S# pin will interrupt the processor and cause it to stop
execution at the next instruction boundary.
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